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81. 发明授权

US06313035B1 Chemical vapor deposition using organometallic precursors 失效
标题翻译：使用有机金属前体的化学气相沉积
公开(公告)号：US06313035B1
公开(公告)日：2001-11-06
申请号：US08660059
申请日：1996-05-31
申请人： Gurtej S. Sandhu , Pierre Fazan
发明人： Gurtej S. Sandhu , Pierre Fazan
IPC分类号： H01L2144
CPC分类号： H01L21/31604 , C23C16/40 , H01L27/10852
摘要： A multi-component layer is deposited on a semiconductor substrate in a semiconductor process. The multi-component layer may be a dielectric layer formed from a gaseous titanium organometallic precursor, reactive silane-based gas and a gaseous oxidant. The multi-component layer may be deposited in a cold wall or hot wall chemical vapor deposition (CVD) reactor, and in the presence or absence of plasma. The multi-component layer may also be deposited using other processes, such as radiant energy or rapid thermal CVD.
摘要翻译：在半导体工艺中在半导体衬底上沉积多组分层。多组分层可以是由气态钛有机金属前体，反应性硅烷基气体和气态氧化剂形成的电介质层。多组分层可以沉积在冷壁或热壁化学气相沉积（CVD）反应器中，并且存在或不存在等离子体。多组分层也可以使用诸如辐射能或快速热CVD的其它过程进行沉积。

82. 发明授权

US6127287A Silicon nitride deposition method for use in forming a memory cell dielectric 失效
标题翻译：用于形成存储单元电介质的氮化硅沉积方法
公开(公告)号：US6127287A
公开(公告)日：2000-10-03
申请号：US956142
申请日：1997-10-22
申请人： Kelly T. Hurley , Li Li , Pierre Fazan , Zhiqiang Wu
发明人： Kelly T. Hurley , Li Li , Pierre Fazan , Zhiqiang Wu
IPC分类号： C23C16/02 , C23C16/34 , H01L21/314 , H01L21/762 , H01L21/31
CPC分类号： H01L21/3144 , C23C16/0272 , C23C16/345 , H01L21/76224
摘要： A method for use in forming a memory cell dielectric includes providing a substrate surface of a memory cell including a silicon based electrode surface. Silicon is predeposited on the electrode surface followed by the deposition of a silicon nitride layer. An incubation time for the start of silicon nitride nucleation at the electrode surface is decreased relative to the incubation time for the start of silicon nitride nucleation when silicon nitride is deposited without predeposition of silicon on the electrode surface. Further, the substrate surface may include one or more component surfaces and when at least a monolayer of silicon is predeposited thereon silicon nitride nucleation at the substrate surface is performed at a substantially equivalent rate independent of the different component surfaces. Alternatively to the predeposition of silicon, the electrode surface may be nitridated prior to deposition of the silicon nitride layer to promote nucleation thereof at an interface between the electrode surface and the silicon nitride layer.
摘要翻译：用于形成存储单元电介质的方法包括提供包括硅基电极表面的存储单元的衬底表面。硅预先沉积在电极表面上，随后沉积氮化硅层。相对于氮化硅成核开始时的温育时间，电极表面开始氮化硅成核的孵育时间降低，而不会在电极表面上沉积硅。此外，基板表面可以包括一个或多个部件表面，并且当至少单层硅预沉积在其上时，基板表面上的氮化硅成核以与不同部件表面无关的基本相等的速率进行。作为硅的预沉积的替代方案，可以在沉积氮化硅层之前将电极表面氮化，以促进其在电极表面和氮化硅层之间的界面处的成核。

83. 发明授权

US5278091A Process to manufacture crown stacked capacitor structures with HSG-rugged polysilicon on all sides of the storage node 失效
标题翻译：在存储节点的所有侧面上制造具有HSG-坚固的多晶硅的冠层叠电容器结构的工艺
公开(公告)号：US5278091A
公开(公告)日：1994-01-11
申请号：US58554
申请日：1993-05-04
申请人： Pierre Fazan , Viju Mathews
发明人： Pierre Fazan , Viju Mathews
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/70
CPC分类号： H01L27/10852 , H01L28/82 , H01L28/84 , H01L28/90 , Y10S438/964
摘要： The present invention develops a container capacitor by forming a first insulative layer over conductive word lines; forming an opening between neighboring conductive word lines; forming a conductive plug between neighboring parallel conductive word lines; forming a planarized blanketing second insulating layer over the first insulative layer and the conductive plug; forming an opening into the second insulating layer, the opening thereby forming a container shape; forming a conductive spacer adjacent the wall of the container form, the conductive spacer having inner and outer surfaces; removing the second insulating layer, thereby exposing the outer surface of the conductive spacer; forming a layer of hemispherical grained conductive material superjacent the inner and outer surfaces of the conductive spacer; forming insulating spacers adjacent the inner and outer surfaces of the hemispherical grained conductive material; patterning the hemispherical grained conductive material to form a separate conductive container structure serving as a first capacitor cell plate; removing the insulating spacers; forming a capacitor cell dielectric layer adjacent and coextensive the conductive container structure and the first insulating layer; and forming a second conductive layer superjacent and coextensive the capacitor cell dielectric layer, the second conductive layer forming a second capacitor cell plate. The process of the present invention can be further modified to form a DRAM double container capacitor storage cell.
摘要翻译：本发明通过在导电字线上形成第一绝缘层来开发容器电容器; 在相邻的导电字线之间形成开口; 在相邻的平行导电字线之间形成导电插塞; 在所述第一绝缘层和所述导电插塞上形成平坦化的覆盖第二绝缘层; 在第二绝缘层中形成开口，由此形成容器形状; 在所述容器形式的壁上形成导电间隔物，所述导电间隔物具有内表面和外表面; 去除第二绝缘层，从而暴露导电间隔物的外表面; 在导电间隔物的内表面和外表面之上形成半球状粒状导电材料层; 形成邻近所述半球形颗粒导电材料的内表面和外表面的绝缘间隔物; 图案化半球状粒状导电材料以形成用作第一电容器单元板的单独的导电容器结构; 去除绝缘垫片; 形成与所述导电容器结构和所述第一绝缘层相邻并共同延伸的电容器单元电介质层; 以及形成第二导电层，所述第二导电层位于所述电容器电介质层的上方并共同延伸，所述第二导电层形成第二电容器单元板。可以进一步修改本发明的方法以形成DRAM双容器电容器存储单元。

84. 发明授权

US5156987A High performance thin film transistor (TFT) by solid phase epitaxial regrowth 失效
标题翻译：高性能薄膜晶体管（TFT）通过固相外延再生长
公开(公告)号：US5156987A
公开(公告)日：1992-10-20
申请号：US812234
申请日：1991-12-18
申请人： Gurtej S. Sandhu , Pierre Fazan
发明人： Gurtej S. Sandhu , Pierre Fazan
IPC分类号： H01L21/20 , H01L21/336 , H01L21/822 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/2022 , H01L21/8221 , H01L29/78654 , Y10S148/109
摘要： The present invention introduces a method to fabricate an active PMOS thin film transistor (or p-ch TFT) having an epitaxially grown channel region for high performance operation characteristics. Typically this p-ch TFT device would be fabricated overlying an NMOS active device, thereby becoming an active load (or pullup) to an NMOS device used is such applications as creating a memory cell in static random access memories (SRAMs). Conductivity types (p-type or n-type) may be interchanged to construct an n-ch TFT coupled with a PMOS active device if so desired. The fabrication of the TFT of the present invention may be used to form a CMOS inverter or simply an active pullup device when integrated into conventional CMOS fabrication processes.
摘要翻译：本发明引入一种制造具有外延生长沟道区域的有源PMOS薄膜晶体管（或p-ch TFT）的方法，用于高性能操作特性。通常，这种p-ch TFT器件将被制造成覆盖在NMOS有源器件上，从而变成所使用的NMOS器件的有源负载（或上拉），这样的应用是在静态随机存取存储器（SRAM）中创建存储器单元。如果需要，可以互换电导型（p型或n型）以构造与PMOS有源器件耦合的n沟道TFT。本发明的TFT的制造可以用于形成CMOS反相器，或者当集成到常规CMOS制造工艺中时，可以简单地形成有源上拉器件。

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