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81. 发明申请

US20090308844A1 MONOLITHIC HIGH ASPECT RATIO NANO-SIZE SCANNING PROBE MICROSCOPE (SPM) TIP FORMED BY NANOWIRE GROWTH 有权
公开(公告)号：US20090308844A1
公开(公告)日：2009-12-17
申请号：US12536156
申请日：2009-08-05
申请人： Guy M. Cohen , Hendrik F. Harmann
发明人： Guy M. Cohen , Hendrik F. Harmann
IPC分类号： C23F1/02
CPC分类号： G01Q70/12 , G01Q60/22
摘要： A scanning probe where the micromachined pyramid tip is extended by the growth of an epitaxial nanowire from the top portion of the tip is disclosed. A metallic particle, such as gold, may terminate the nanowire to realize an apertureless near-field optical microscope probe.

82. 发明申请

US20090117694A1 NANOWIRE BASED NON-VOLATILE FLOATING-GATE MEMORY 有权
标题翻译：基于NANOWIRE的非易失性浮动门存储器
公开(公告)号：US20090117694A1
公开(公告)日：2009-05-07
申请号：US12121044
申请日：2008-05-15
申请人： Guy M. Cohen
发明人： Guy M. Cohen
IPC分类号： H01L21/8232 , H01L21/36
CPC分类号： H01L29/7881 , B82Y10/00 , H01L21/28273 , H01L29/0676 , H01L29/42332 , H01L29/7887 , H01L29/94 , Y10S977/762 , Y10S977/814 , Y10S977/832 , Y10S977/891 , Y10S977/943
摘要： A non-volatile memory transistor with a nanocrystal-containing floating gate formed by nanowires is disclosed. The nanocrystals are formed by the growth of short nanowires over a crystalline program oxide. As a result, the nanocrystals are single-crystals of uniform size and single-crystal orientation.
摘要翻译：公开了一种具有由纳米线形成的含纳米晶体的浮栅的非易失性存储晶体管。通过在结晶程序氧化物上生长短的纳米线形成纳米晶体。结果，纳米晶体是均匀尺寸和单晶取向的单晶。

83. 发明授权

US07391074B2 Nanowire based non-volatile floating-gate memory 失效
标题翻译：纳米线非挥发性浮栅存储器
公开(公告)号：US07391074B2
公开(公告)日：2008-06-24
申请号：US11195889
申请日：2005-08-03
申请人： Guy M. Cohen
发明人： Guy M. Cohen
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , B82Y10/00 , H01L21/28273 , H01L29/0676 , H01L29/42332 , H01L29/7887 , H01L29/94 , Y10S977/762 , Y10S977/814 , Y10S977/832 , Y10S977/891 , Y10S977/943
摘要： A non-volatile memory transistor with a nanocrystal-containing floating gate formed by nanowires is disclosed. The nanocrystals are formed by the growth of short nanowires over a crystalline program oxide. As a result, the nanocrystals are single-crystals of uniform size and single-crystal orientation.
摘要翻译：公开了一种具有由纳米线形成的含纳米晶体的浮栅的非易失性存储晶体管。通过在结晶程序氧化物上生长短的纳米线形成纳米晶体。结果，纳米晶体是均匀尺寸和单晶取向的单晶。

84. 发明授权

US06444578B1 Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices 有权
标题翻译：用于减少浅结和薄SOI电子器件中Si消耗的自对准硅化物工艺
公开(公告)号：US06444578B1
公开(公告)日：2002-09-03
申请号：US09791024
申请日：2001-02-21
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin K. Chan , Guy M. Cohen , Kathryn Wilder Guarini , James M. Harper , Christian Lavoie , Paul M. Solomon
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin K. Chan , Guy M. Cohen , Kathryn Wilder Guarini , James M. Harper , Christian Lavoie , Paul M. Solomon
IPC分类号： H01L2144
CPC分类号： H01L21/28518
摘要： The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a M—Si or M—Si—Ge alloy, where M is Co, Ni or CoNi and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.
摘要翻译：本发明涉及在采用M-Si或M-Si-Ge合金的自对准硅化物工艺中降低Si消耗的方法，其中M是Co，Ni或CoNi以及Si的覆盖层。本发明特别可用于最大限度地减少浅结和薄绝缘体上硅（SOI）电子器件中的Si消耗。

85. 发明授权

US08685823B2 Nanowire field effect transistor device 有权
标题翻译：纳米线场效应晶体管器件
公开(公告)号：US08685823B2
公开(公告)日：2014-04-01
申请号：US13292336
申请日：2011-11-09
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Jeffrey W. Sleight
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78696 , Y10S977/938
摘要： A method for forming a field effect transistor device includes forming a nanowire suspended above a substrate, forming a dummy gate stack on a portion of the substrate and around a portion of the nanowire, removing exposed portions of the nanowire, epitaxially growing nanowire extension portions from exposed portions of the nanowire, depositing a layer of semiconductor material over exposed portions of the substrate, the dummy gate stack and the nanowire extension portions, and removing portions of the semiconductor material to form sidewall contact regions arranged adjacent to the dummy gate stack and contacting the nanowire extension portions.
摘要翻译：一种用于形成场效应晶体管器件的方法包括形成悬浮在衬底上的纳米线，在衬底的一部分和纳米线的一部分周围形成虚拟栅极堆叠，从纳米线的外延生长纳米线延伸部分的外延生长暴露的纳米线部分，在衬底的暴露部分，伪栅极堆叠和纳米线延伸部分上沉积半导体材料层，以及去除半导体材料的部分以形成邻近虚拟栅极堆叠布置的侧壁接触区域，纳米线延伸部分。

86. 发明授权

US08536563B2 Nanowire field effect transistors 有权
标题翻译：纳米线场效应晶体管
公开(公告)号：US08536563B2
公开(公告)日：2013-09-17
申请号：US12884707
申请日：2010-09-17
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L29/06
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/84 , H01L29/0673 , H01L29/42392 , H01L29/4966 , H01L29/513 , H01L29/66439 , H01L29/78696
摘要： A method for forming a nanowire field effect transistor (FET) device including forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a substrate, patterning a first hardmask layer over the second SOI portion, forming a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer, forming a second suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire, and removing the second hardmask layer.
摘要翻译：一种用于形成纳米线场效应晶体管（FET）器件的方法，包括形成绝缘体上硅（SOI）焊盘区域，第二SOI焊盘区域，第三SOI焊盘区域，将第一SOI焊盘区域连接到第一SOI焊盘区域的第一SOI部分第二SOI焊盘区域和将第二SOI焊盘区域连接到衬底上的第三SOI焊盘区域的第二SOI部分，在第二SOI部分上形成第一硬掩模层，在半导体衬底上形成第一悬浮的纳米线，形成第一围绕第一悬浮纳米线的一部分构造栅极结构，在第一栅极结构和第一悬置纳米线上图案化第二硬掩模层，去除第一硬掩模层，在半导体衬底上形成第二悬浮纳米线，在第二栅极结构周围形成第二栅极结构第二悬浮纳米线的一部分，以及去除第二硬掩模层。

87. 发明申请

US20130175597A1 NANOWIRE FLOATING GATE TRANSISTOR 有权
标题翻译： NANOWIRE浮动门极晶体管
公开(公告)号：US20130175597A1
公开(公告)日：2013-07-11
申请号：US13344517
申请日：2012-01-05
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： G11C11/5671 , H01L21/28273 , H01L29/0673 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/7881
摘要： A floating gate transistor, memory cell, and method of fabricating a device. The floating gate transistor includes one or more gated wires substantially cylindrical in form. The floating gate transistor includes a first gate dielectric layer at least partially covering the gated wires. The floating gate transistor further includes a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer. The floating gate transistor also includes a second gate dielectric layer covering the plurality of gate crystals and the first gate dielectric layer.
摘要翻译：浮栅晶体管，存储单元及其制造方法。浮栅晶体管包括一个或多个基本上圆柱形的选通线。浮置栅极晶体管包括至少部分地覆盖选通导线的第一栅极电介质层。浮置栅极晶体管还包括不连续地布置在第一栅极介电层上的多个栅极晶体。浮栅晶体管还包括覆盖多个栅极晶体和第一栅极介电层的第二栅极电介质层。

88. 发明授权

US08445337B2 Generation of multiple diameter nanowire field effect transistors 有权
标题翻译：生成多直径纳米线场效应晶体管
公开(公告)号：US08445337B2
公开(公告)日：2013-05-21
申请号：US12778517
申请日：2010-05-12
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L21/00
CPC分类号： H01L29/0669 , B82Y10/00 , H01L21/84 , H01L27/1203 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： A method of modifying a wafer having semiconductor disposed on an insulator is provided and includes establishing first and second regions of the wafer with different initial semiconductor thicknesses, forming pairs of semiconductor pads connected via respective nanowire channels at each of the first and second regions and reshaping the nanowire channels into nanowires each having a respective differing thickness reflective of the different initial semiconductor thicknesses at each of the first and second regions.
摘要翻译：提供了一种修改具有设置在绝缘体上的半导体的晶片的方法，包括以不同的初始半导体厚度建立晶片的第一和第二区域，形成经由每个第一和第二区域上的相应纳米线通道连接的半导体焊盘对，并重塑纳米线通道进入纳米线，每个纳米线具有反映第一和第二区域中的每一个处的不同初始半导体厚度的各自不同的厚度。

89. 发明申请

US20130017673A1 GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS 有权
标题翻译：多直径纳米场效应晶体管的生成
公开(公告)号：US20130017673A1
公开(公告)日：2013-01-17
申请号：US13610223
申请日：2012-09-11
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Jeffrey W. Sleight
IPC分类号： H01L21/84 , B82Y99/00
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/302 , H01L21/3247 , H01L29/045 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming first and second nanowire channels connected at each end to semiconductor pads at first and second wafer regions, respectively, with second nanowire channel sidewalls being misaligned relative to a crystallographic plane of the semiconductor more than first nanowire channel sidewalls and displacing the semiconductor toward an alignment condition between the sidewalls and the crystallographic plane such that thickness differences between the first and second nanowire channels reflect the greater misalignment of the second nanowire channel sidewalls.
摘要翻译：提供了修改具有设置在绝缘体上的半导体的晶片的方法，并且包括分别在第一和第二晶片区域处形成分别连接到半导体焊盘的第一和第二纳米线通道，其中第二纳米线通道侧壁相对于晶体学不对准半导体的平面超过第一纳米线通道侧壁并将半导体移向侧壁和结晶平面之间的对准状态，使得第一和第二纳米线通道之间的厚度差异反映了第二纳米线通道侧壁的较大的未对准。

90. 发明申请

US20120331593A1 PRODUCTION SCALE FABRICATION METHOD FOR HIGH RESOLUTION AFM TIPS 失效
公开(公告)号：US20120331593A1
公开(公告)日：2012-12-27
申请号：US13608396
申请日：2012-09-10
申请人： Guy M. Cohen , Mark C. Reuter , Brent A. Wacaser , Maha M. Khayyat
发明人： Guy M. Cohen , Mark C. Reuter , Brent A. Wacaser , Maha M. Khayyat
IPC分类号： G01Q60/38 , B82Y40/00
CPC分类号： G01Q70/12 , G01Q60/38
摘要： A method of fabricating high resolution atomic force microscopy (AFM) tips including a single semiconductor nanowire grown at an apex of a semiconductor pyramid of each AFM tip is provided. The semiconductor nanowire that is grown has a controllable diameter and a high aspect ratio, without significant tapering from the tip of the semiconductor nanowire to its base. The method includes providing an AFM probe including a semiconductor cantilever having a semiconductor pyramid extending upward from a surface of said semiconductor cantilever. The semiconductor pyramid has an apex. A patterned oxide layer is formed on the AFM probe. The patterned oxide layer has an opening that exposes the apex of the semiconductor pyramid. A single semiconductor nanowire is grown on the exposed apex of the semiconductor pyramid utilizing a non-oxidized Al seed material as a catalyst for nanowire growth.

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