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81. 发明授权

US07523268B2 Reducing number of rejected snoop requests by extending time to respond to snoop request 有权
标题翻译：通过延长响应窥探请求的时间来减少被拒绝的窥探请求数
公开(公告)号：US07523268B2
公开(公告)日：2009-04-21
申请号：US12114790
申请日：2008-05-04
申请人： Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is dispatched to a selector upon entering a bottom latch in the pipeline. The stall/reorder unit is not informed as to whether the dispatched snoop request is accepted by an arbitration mechanism for several clock cycles after the dispatch occurred. A copy of the dispatched snoop request is stored in a top latch in an overrun pipeline of latches in the first unit upon dispatching the snoop request. By maintaining information about the snoop request, the snoop request may be dispatched again to the selector in case the dispatched snoop request was rejected thereby increasing the chance that the snoop request will ultimately be accepted.
摘要翻译：用于减少拒绝的窥探请求数量的缓存，系统和方法。如果失速/重新排序单元未满，则在失速/重新排序单元中的锁存器管线中的第一可用锁存器中输入进入的窥探请求。输入的窥探请求在进入管道中的底部闩锁时被调度到选择器。失速/重新排序单元不知道发送后发送的几个时钟周期是否由仲裁机制接受发送的窥探请求。调度窥探请求的副本在调度窥探请求时被存储在第一单元中的锁存器的溢出管道中的顶部锁存器中。通过维护关于窥探请求的信息，可以在被发送的窥探请求被拒绝的情况下再次发送到选择器的窥探请求，从而增加窥探请求将最终被接受的机会。

82. 发明授权

US07475195B2 Data processing system, cache system and method for actively scrubbing a domain indication 失效
标题翻译：数据处理系统，缓存系统和方法，用于主动清理域指示
公开(公告)号：US07475195B2
公开(公告)日：2009-01-06
申请号：US11136651
申请日：2005-05-24
申请人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F12/0822
摘要： Scrubbing logic in a local coherency domain issues to at least one cache hierarchy in a remote coherency domain a domain reset request that forces invalidation of any cached copy of a target memory block then held in said remote coherency domain. A coherency response to said domain reset request is received. In response to said coherency response indicating that said target memory block is not cached in said remote coherency domain, a domain indication of said local coherency domain is updated to indicate that said target memory block is cached, if at all, only within said local coherency domain.
摘要翻译：本地一致性域中的擦除逻辑向远程一致性域中的至少一个高速缓存层次结构发出一个域重置请求，该请求强制所保存在所述远程一致性域中的目标存储器块的任何高速缓存副本的无效。接收到对所述域重置请求的一致性响应。响应于所述相关性响应指示所述目标存储器块未被高速缓存在所述远程一致性域中，所述本地一致性域的域指示被更新以指示所述目标存储器块被缓存，如果完全只在所述局部一致性内域。

83. 发明申请

US20080215824A1 CACHE MEMORY, PROCESSING UNIT, DATA PROCESSING SYSTEM AND METHOD FOR FILTERING SNOOPED OPERATIONS 失效
标题翻译：高速缓存存储器，处理单元，数据处理系统和过滤操作的方法
公开(公告)号：US20080215824A1
公开(公告)日：2008-09-04
申请号：US12106102
申请日：2008-04-18
申请人： BENJIMAN L. GOODMAN , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： BENJIMAN L. GOODMAN , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0831
摘要： A cache coherent data processing system includes at least a first cache memory supporting a first processing unit and a second cache memory supporting a second processing unit. The first cache memory includes a cache array and a cache directory of contents of the cache array. In response to the first cache memory detecting on an interconnect a broadcast operation that specifies a request address, the first cache memory determines from the operation a type of the operation and a coherency state associated with the request address. In response to determining the type and the coherency state, the first cache memory filters out the broadcast operation without accessing the cache directory.
摘要翻译：高速缓存一致数据处理系统至少包括支持第一处理单元的第一高速缓冲存储器和支持第二处理单元的第二高速缓冲存储器。第一缓存存储器包括缓存阵列和高速缓存阵列的内容的高速缓存目录。响应于第一高速缓冲存储器在互连上检测指定请求地址的广播操作，第一高速缓冲存储器从操作中确定与请求地址相关联的操作类型和一致性状态。响应于确定类型和一致性状态，第一高速缓存存储器过滤掉广播操作而不访问高速缓存目录。

84. 发明授权

US10235215B2 Memory lock mechanism for a multiprocessor system 有权
公开(公告)号：US10235215B2
公开(公告)日：2019-03-19
申请号：US12024169
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
IPC分类号： G06F17/30 , G06F9/52 , G06F9/30
摘要： A memory lock mechanism within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory of the multiprocessor system. In response to a request for accessing the data block by a processing unit within the multiprocessor system, a determination is made by a memory controller whether or not the lock control section of the data block has been set. If the lock control section of the data block has been set, the request for accessing the data block is denied. Otherwise, if the lock control section of the data block has not been set, the lock control section of the data block is set, and the request for accessing the data block is allowed.

85. 发明授权

US08312220B2 Mode-based castout destination selection 失效
标题翻译：基于模式的castout目的地选择
公开(公告)号：US08312220B2
公开(公告)日：2012-11-13
申请号：US12420933
申请日：2009-04-09
申请人： Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Phillip G. Williams , Jeffrey A. Stuecheli
发明人： Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Phillip G. Williams , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/12
摘要： In response to a data request of a first of a plurality of processing units, the first processing unit selects a victim cache line to be castout from the lower level cache of the first processing unit and determines whether a mode is set. If not, the first processing unit issues on the interconnect fabric an LCO command identifying the victim cache line and indicating that a lower level cache is the intended destination. If the mode is set, the first processing unit issues a castout command with an alternative intended destination. In response to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from its lower level cache, and the victim cache line is held elsewhere in the data processing system. The mode can be set to inhibit castouts to system memory, for example, for testing.
摘要翻译：响应于多个处理单元中的第一处理单元的数据请求，第一处理单元从第一处理单元的较低级高速缓存中选择要丢弃的牺牲高速缓存行，并且确定是否设置了模式。如果不是，则第一处理单元在互连结构上发出识别受害者高速缓存行的LCO命令，并指示较低级别的高速缓存是预期的目的地。如果模式被设置，则第一处理单元发出具有替代预定目的地的停顿命令。响应于指示LCO命令成功的LCO命令的一致性响应，第一处理单元从其较低级高速缓存中去除受害者高速缓存行，并且将受害者高速缓存行保持在数据处理系统的其他地方。该模式可以设置为抑制系统内存的丢弃，例如进行测试。

86. 发明授权

US08209489B2 Victim cache prefetching 失效
标题翻译：受害者缓存预取
公开(公告)号：US08209489B2
公开(公告)日：2012-06-26
申请号：US12256064
申请日：2008-10-22
申请人： Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
发明人： Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0897 , Y02D10/13
摘要： A processing unit for a multiprocessor data processing system includes a processor core and a cache hierarchy coupled to the processor core to provide low latency data access. The cache hierarchy includes an upper level cache coupled to the processor core and a lower level victim cache coupled to the upper level cache. In response to a prefetch request of the processor core that misses in the upper level cache, the lower level victim cache determines whether the prefetch request misses in the directory of the lower level victim cache and, if so, allocates a state machine in the lower level victim cache that services the prefetch request by issuing the prefetch request to at least one other processing unit of the multiprocessor data processing system.
摘要翻译：用于多处理器数据处理系统的处理单元包括处理器核心和耦合到处理器核心的高速缓存层级以提供低延迟数据访问。高速缓存层级包括耦合到处理器核心的高级缓存和耦合到高级缓存的较低级别的牺牲缓存。响应于在高级缓存中丢失的处理器核心的预取请求，较低级别的受害者缓存确定预取请求是否丢失在较低级别的受害者缓存的目录中，并且如果是，则在下级缓存中分配状态机通过向多处理器数据处理系统的至少一个其他处理单元发出预取请求来服务于预取请求。

87. 发明授权

US08205136B2 Fault tolerant encoding of directory states for stuck bits 有权
标题翻译：卡位的目录状态的容错编码
公开(公告)号：US08205136B2
公开(公告)日：2012-06-19
申请号：US12189808
申请日：2008-08-12
申请人： Robert H. Bell, Jr. , Guy L. Guthrie , William J. Starke
发明人： Robert H. Bell, Jr. , Guy L. Guthrie , William J. Starke
IPC分类号： G11C29/00
CPC分类号： G11C29/832 , G06F11/1064
摘要： A method of handling a stuck bit in a directory of a cache memory, by defining multiple binary encodings to indicate a defective cache state, detecting an error in a tag stored in a member of the directory (wherein the tag at least includes an address field, a state field and an error-correction field), determining that the error is associated with a stuck bit of the directory member, and writing new state information to the directory member which is selected from one of the binary encodings based on a field location of the stuck bit within the directory member. The multiple binary encodings may include a first binary encoding when the stuck bit is in the address field, a second binary encoding when the stuck bit is in the state field, and a third binary encoding when the stuck bit is in the error-correction field. The new state information may also further be selected based on the value of the stuck bit, e.g., a state bit corresponding to the stuck bit is assigned a bit value from the new state information which matches the value of the stuck bit.
摘要翻译：一种通过定义多个二进制编码来指示缺陷高速缓存状态来处理高速缓冲存储器的目录中的卡住位的方法，检测存储在目录成员中的标签中的错误（其中标签至少包括地址字段，状态字段和纠错字段），确定错误与目录成员的卡住位相关联，并且基于字段位置将新状态信息写入从二进制编码之一中选择的目录成员的目录成员中的卡住位。多个二进制编码可以包括当卡住位在地址字段中时的第一二进制编码，当卡位位于状态字段时的第二二进制编码，以及当卡位位于错误校正字段中时的第三二进制编码。还可以基于卡住位的值进一步选择新的状态信息，例如，对应于该卡住位的状态位从与该卡位的值匹配的新状态信息中分配一位值。

88. 发明申请

US20100262778A1 Empirically Based Dynamic Control of Transmission of Victim Cache Lateral Castouts 有权
标题翻译：基于经验的动态控制受害者缓存横向铸件传动
公开(公告)号：US20100262778A1
公开(公告)日：2010-10-14
申请号：US12421180
申请日：2009-04-09
申请人： Robert A. Cargnoni , Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
发明人： Robert A. Cargnoni , Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0862 , G06F12/127 , G06F2212/6026
摘要： In response to a data request, a victim cache line is selected for castout from a lower level cache, and a target lower level cache of one of the plurality of processing units is selected. A determination is made whether the selected target lower level cache has provided more than a threshold number of retry responses to lateral castout (LCO) commands of the first lower level cache, and if so, a different target lower level cache is selected. The first processing unit thereafter issues a LCO command on the interconnect fabric. The LCO command identifies the victim cache line to be castout and indicates that the target lower level cache is an intended destination of the victim cache line. In response to a successful coherence response to the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.
摘要翻译：响应于数据请求，选择从较低级别高速缓冲存储器进行丢弃的受害者高速缓存行，并且选择多个处理单元之一的目标下级高速缓存。确定所选择的目标下层高速缓存是否为第一较低级别高速缓存的横向转移（LCO）命令提供了超过阈值数量的重试响应，如果是，则选择不同的目标低级高速缓存。此后，第一处理单元在互连结构上发出LCO命令。 LCO命令标识要丢弃的受害者缓存行，并指示目标下级缓存是受害缓存行的预期目标。响应于对LCO命令的成功的一致性响应，从第一低级缓存中移除受害者高速缓存行并保存在第二较低级缓存中。

89. 发明授权

US07761631B2 Data processing system, method and interconnect fabric supporting destination data tagging 失效
标题翻译：数据处理系统，方法和互连结构支持目标数据标记
公开(公告)号：US07761631B2
公开(公告)日：2010-07-20
申请号：US12117539
申请日：2008-05-08
申请人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
发明人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F13/42 , G06F13/00
CPC分类号： G06F15/16
摘要： A data processing system includes a plurality of communication links and a plurality of processing units including a local master processing unit. The local master processing unit includes interconnect logic that couples the processing unit to one or more of the plurality of communication links and an originating master coupled to the interconnect logic. The originating master originates an operation by issuing a write-type request on at least one of the one or more communication links, receives from a snooper in the data processing system a destination tag identifying a route to the snooper, and, responsive to receipt of the combined response and the destination tag, initiates a data transfer including a data payload and a data tag identifying the route provided within the destination tag.
摘要翻译：数据处理系统包括多个通信链路和包括本地主处理单元的多个处理单元。本地主处理单元包括将处理单元耦合到多个通信链路中的一个或多个以及耦合到互连逻辑的始发主机的互连逻辑。始发主机通过在一个或多个通信链路中的至少一个发出写入请求来发起操作，从数据处理系统中的窥探者接收标识到窥探者的路由的目的地标签，并且响应于接收到组合响应和目的地标签，发起包括数据有效载荷和标识目的地标签内提供的路由的数据标签的数据传输。

90. 发明申请

US20100100682A1 Victim Cache Replacement 有权
标题翻译：受害者缓存替换
公开(公告)号：US20100100682A1
公开(公告)日：2010-04-22
申请号：US12256002
申请日：2008-10-22
申请人： Guy L. Guthrie , Thomas L. Jeremiah , William L. McNeil , Piyush C. Patel , William J. Starke , Jeffrey A. Stuecheli
发明人： Guy L. Guthrie , Thomas L. Jeremiah , William L. McNeil , Piyush C. Patel , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/128 , G06F2212/1028 , Y02D10/13
摘要： A data processing system includes a processor core having an associated upper level cache and a lower level victim cache. In response to a memory access request of the processor core that specifies a non-modifying access to a target coherency granule, a determination is made whether the memory access request hits or misses in a directory of the lower level victim cache. In response to determining that the memory access request hits in the lower level victim cache in a data-valid coherence state, the lower level victim cache provides the target coherency granule of the memory access request to the upper level cache. The lower level victim cache preserves the target coherency granule in the lower level victim cache in a shared coherence state if the memory access request is of a first type and invalidates the target coherency granule if the memory access request is of a second type.
摘要翻译：数据处理系统包括具有相关联的高级缓存和较低级别的受害缓存的处理器核心。响应于指定对目标一致性粒子的不修改访问的处理器核心的存储器访问请求，确定存储器访问请求是否在较低级别的受害缓存的目录中命中或丢失。响应于确定存储器访问请求在数据有效的相干状态中击中较低级别的受害者高速缓存，则较低级别的受害者缓存将存储器访问请求的目标一致性颗粒提供给高级缓存。如果存储器访问请求是第一类型，则较低级别的受害者缓存在共享相干状态下保留较低级别的受害者缓存中的目标一致性粒子，如果存储器访问请求是第二类型，则使目标一致性粒子无效。

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