专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US5583060A Method for manufacturing field effect controlled semiconductor components 失效
标题翻译：制造场效应控制半导体元件的方法
公开(公告)号：US5583060A
公开(公告)日：1996-12-10
申请号：US552702
申请日：1995-11-03
申请人： Helmut Hertrich , Helmut Strack , Jenoe Tihanyi
发明人： Helmut Hertrich , Helmut Strack , Jenoe Tihanyi
IPC分类号： H01L21/331 , H01L21/336 , H01L29/10 , H01L29/739 , H01L29/78 , H01L21/8224 , H01L21/8234
CPC分类号： H01L29/7802 , H01L29/1095 , H01L29/6634 , H01L29/66348 , H01L29/7396 , H01L29/7397 , H01L29/7813 , H01L29/41766 , Y10S148/126
摘要： The base zones of MOSFETs and IGBTs are generated by implanting dopants of the second conductivity type into the surface of a first layer of the first conductivity type, and a second layer of the first conductivity type is deposited thereon. During the deposition, the dopants diffuse up to the surface of the second layer and form base zones. The base zones are thereby provided with a laterally expanded region of high conductivity under the surface through which the minority carriers can flow off to the source electrode with low voltage drop.
摘要翻译： MOSFET和IGBT的基极区通过将第二导电类型的掺杂剂注入第一导电类型的第一层的表面中而沉积第一导电类型的第二层来产生。在沉积期间，掺杂剂扩散到第二层的表面并形成基区。因此，基部区域在其表面下设置有高度导电性的横向扩张区域，少数载流子可以通过该横向膨胀区域以低电压降流到源电极。

82. 发明授权

US5302537A Manufacturing method for a low voltage power MISFET utilizing only three masks 失效
标题翻译：仅使用三个掩模的低电压功率MISFET的制造方法
公开(公告)号：US5302537A
公开(公告)日：1994-04-12
申请号：US976189
申请日：1992-11-13
申请人： Helmut Strack
发明人： Helmut Strack
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/40 , H01L21/265
CPC分类号： H01L29/405 , H01L23/3171 , H01L29/66727 , H01L29/7811 , H01L29/0638 , H01L29/402 , H01L29/42376 , H01L2924/0002 , Y10S148/126 , Y10S438/958
摘要： A manufacturing method for a low-voltage power MISFET which utilizes only three masks (photosteps). In the first step, a polysilicon layer (3) is structured and a cell field and edge zones are produced. An oxide layer (2) is then applied, this being opened in the second photostep above the cells and the edge zones and between the edge (4) and the cells. A metal layer is then applied, this being interrupted between the cells and the edge (4) with the third photostep. Field plates and a channel stopper (9) are thus produced. As last step, a weakly conductive layer (20) is applied onto the entire surface.
摘要翻译：一种低电压功率MISFET的制造方法，仅使用三个掩模（光步）。在第一步骤中，构造多晶硅层（3）并产生单元区域和边缘区域。然后施加氧化物层（2），其在细胞和边缘区域之上以及边缘（4）和细胞之间的第二光步中打开。然后施加金属层，这在金属层和边缘（4）之间被第三次照相中断。因此制造了场板和通道挡块（9）。作为最后一步，将弱导电层（20）施加到整个表面上。

83. 发明授权

US4079406A Thyristor having a plurality of emitter shorts in defined spacial relationship 失效
标题翻译：晶闸管具有多个限定空间关系的发射极短路
公开(公告)号：US4079406A
公开(公告)日：1978-03-14
申请号：US749171
申请日：1976-12-09
申请人： Joachim Burtscher , Helmut Strack
发明人： Joachim Burtscher , Helmut Strack
IPC分类号： H01L29/08 , H01L29/74
CPC分类号： H01L29/0839
摘要： A thyristor device is provided with a shorted emitter structure in which the shorts are circularly formed zones of the base zone which extend through the emitter zone into electrical contact with the emitter electrode. Each of these zones is circular in cross-section and of a diameter which is less than 20.mu.m. These zones have a spacing from each other from center to center which is such that the ratio of this spacing to the diameter of a circular area is greater than 3.
摘要翻译：晶闸管器件具有短路发射极结构，其中短路是穿过发射极区延伸穿过发射极电极的基极区的圆形区域。这些区域中的每个区域的横截面为圆形，直径小于20μm。这些区域具有从中心到中心彼此间隔的距离，使得该间隔与圆形区域的直径之比大于3。

84. 发明授权

US08415219B2 Method of manufacturing a DMOS trench transistor 有权
标题翻译：制造DMOS沟槽晶体管的方法
公开(公告)号：US08415219B2
公开(公告)日：2013-04-09
申请号：US11638612
申请日：2006-12-13
申请人： Franz Hirler , Helmut Strack
发明人： Franz Hirler , Helmut Strack
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L29/0847 , H01L29/086 , H01L29/1604 , H01L29/165 , H01L29/41766 , H01L29/7813
摘要： To attain a comparatively high breakdown voltage at a high avalanche strength and with the physical size simultaneously being as small as possible, the invention proposes constructing a transistor device in a semiconductor material region in which a first source/drain region is used as a source region and in which the source region has a comparatively reduced surface charge or surface charge density.
摘要翻译：为了在高雪崩强度下获得相当高的击穿电压并且物理尺寸同时尽可能小，本发明提出在其中使用第一源极/漏极区域作为源极区域的半导体材料区域中构造晶体管器件并且其中源区具有相对减小的表面电荷或表面电荷密度。

85. 发明申请

US20100264523A1 Panel, Semiconductor Device and Method for the Production Thereof 有权
标题翻译：面板，半导体器件及其制造方法
公开(公告)号：US20100264523A1
公开(公告)日：2010-10-21
申请号：US12828327
申请日：2010-07-01
申请人： Adolf Koller , Horst Theuss , Ralf Otremba , Josef Hoeglauer , Helmut Strack , Reinhard Ploss
发明人： Adolf Koller , Horst Theuss , Ralf Otremba , Josef Hoeglauer , Helmut Strack , Reinhard Ploss
IPC分类号： H01L23/552 , H01L23/485
CPC分类号： H01L23/552 , H01L23/3114 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/82 , H01L24/97 , H01L2224/05001 , H01L2224/05022 , H01L2224/05147 , H01L2224/05572 , H01L2224/05647 , H01L2224/16225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/49171 , H01L2224/92244 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/12041 , H01L2924/12044 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/15787 , H01L2924/19107 , H01L2924/3025 , H01L2224/82 , H01L2924/00 , H01L2224/45099
摘要： A panel has a baseplate with an upper first metallic layer and a multiplicity of a vertical semiconductor components. The vertical semiconductor components in each case have a first side with a first load electrode and a control electrode and an opposite second side with a second load electrode. The second side of the semiconductor components is in each case mounted on the metallic layer of the baseplate. The semiconductor components are arranged in such a way that edge sides of adjacent semiconductor components are separated from one another. A second metallic layer is arranged in separating regions between the semiconductor components.
摘要翻译：面板具有具有上部第一金属层和多个垂直半导体部件的基板。每种情况下的垂直半导体部件具有第一侧，其具有第一负载电极和控制电极，而第二侧具有第二负载电极。半导体部件的第二面分别安装在基板的金属层上。半导体部件被配置成使得相邻的半导体部件的边缘彼此分离。第二金属层布置在半导体部件之间的分离区域中。

86. 发明申请

US20070023881A1 Semiconductor Wafer with a Wiring Structure, a Semiconductor Component, and Methods for Their Production 有权
标题翻译：具有接线结构的半导体晶片，半导体元件及其制造方法
公开(公告)号：US20070023881A1
公开(公告)日：2007-02-01
申请号：US11427204
申请日：2006-06-28
申请人： Helmut Strack
发明人： Helmut Strack
IPC分类号： H01L23/02 , H01L21/00
CPC分类号： H01L21/6835 , H01L21/76256 , H01L21/76834 , H01L21/76838 , H01L29/417 , H01L29/456 , H01L29/861 , H01L2221/6834 , H01L2221/6835 , H01L2221/68363 , H01L2924/0002 , Y10S438/977 , H01L2924/00
摘要： A semiconductor wafer is provided with a wiring structure, and semiconductor chip positions arranged in rows and columns. The semiconductor wafer has at least one coating (6) as a self-supporting dimensionally stable substrate layer (4), and/or as a wiring structure composed of conductive, high-temperature-resistant material. The coating material (6) of the substrate layer (4) and/or of the wiring structure has a ternary carbide and/or a ternary nitride and/or carbon.
摘要翻译：半导体晶片设置有布线结构，半导体芯片位置配置成行和列。半导体晶片具有至少一个作为自支撑尺寸稳定的基板层（4）的涂层（6），和/或作为由导电的耐高温材料构成的布线结构。衬底层（4）和/或布线结构的涂层材料（6）具有三元碳化物和/或三元氮化物和/或碳。

87. 发明申请

US20060180932A1 Component arrangement for series terminal for high-voltage applications 审中-公开
标题翻译：用于高压应用的串联端子的组件布置
公开(公告)号：US20060180932A1
公开(公告)日：2006-08-17
申请号：US11328595
申请日：2006-01-10
申请人： Ralf Otremba , Khalil Hosseini , Helmut Strack
发明人： Ralf Otremba , Khalil Hosseini , Helmut Strack
IPC分类号： H01L23/52
CPC分类号： H01L24/72 , H01L23/051 , H01L23/4334 , H01L23/49562 , H01L24/48 , H01L25/117 , H01L2224/48472 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/09701 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/1815 , H01L2924/19043 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： One embodiment of the invention relates to a component arrangement having a semiconductor chip, a chip carrier, a contact piece and a package. The semiconductor chip includes a first load terminal, a second load terminal and a control terminal, with the first load terminal and the second load terminal being arranged on mutually opposite sides of the semiconductor chip. The semiconductor chip is arranged on the chip carrier and is electrically and thermally conductively connected to the first load terminal. The contact piece is arranged on the second load terminal and is electrically and thermally conductively connected to it. The package is formed from a dielectric compound, which surrounds the semiconductor chip, the chip carrier and the contact piece. The chip carrier is exposed on a first side of the package, the contact piece is exposed on a second side of the package opposite the first side. A connecting leg is passed out of the package and is electrically conductively connected to the control terminal. One embodiment of the invention furthermore relates to a component cascade, in which a plurality of component arrangements are arranged on one another in the form of a stack.
摘要翻译：本发明的一个实施例涉及具有半导体芯片，芯片载体，接触片和封装的部件布置。半导体芯片包括第一负载端子，第二负载端子和控制端子，其中第一负载端子和第二负载端子布置在半导体芯片的相对的相对侧上。半导体芯片布置在芯片载体上并且电和热导电地连接到第一负载端子。接触件布置在第二负载端子上，并且与导电连接。封装由围绕半导体芯片，芯片载体和接触片的电介质化合物形成。芯片载体暴露在封装的第一侧上，接触件暴露在与第一侧相对的封装的第二侧上。连接腿从包装件中流出并与导电连接到控制端子。本发明的一个实施例还涉及一种组件级联，其中多个组件布置以堆叠的形式彼此布置。

88. 发明授权

US06225643B1 SOI cell and method for producing it 有权
标题翻译： SOI电池及其制造方法
公开(公告)号：US06225643B1
公开(公告)日：2001-05-01
申请号：US09158248
申请日：1998-09-22
申请人： Jenoe Tihanyi , Helmut Strack
发明人： Jenoe Tihanyi , Helmut Strack
IPC分类号： H01L2904
CPC分类号： H01L29/7802 , H01L29/0649 , H01L29/0653 , H01L29/1095 , H01L29/41766 , H01L29/6634 , H01L29/7395 , H01L29/7396
摘要： An SOI cell includes a semiconductor body having at least one insulator layer. A polycrystalline zone doped with a dopant of a first conductivity type is grown on the insulator layer. The polycrystalline zone is adjoined outside the region of the insulator layer by a semiconductor region, which is doped with the dopant of the first conduction type that has been diffused out of the polycrystalline zone. A dopant source having a dopant of a second conductivity type is also provided. A zone having the dopant of the second conductivity type is formed by diffusing the dopant out of the dopant source.
摘要翻译： SOI单元包括具有至少一个绝缘体层的半导体本体。在绝缘体层上生长掺杂有第一导电类型的掺杂剂的多晶区。多晶区域通过半导体区域与绝缘体层的区域相邻，该半导体区域掺杂有已经扩散到多晶区域的第一导电类型的掺杂剂。还提供了具有第二导电类型的掺杂剂的掺杂剂源。通过将掺杂剂从掺杂剂源扩散出来，形成具有第二导电类型的掺杂剂的区域。

89. 发明授权

US06184555B2 Field effect-controlled semiconductor component 有权
标题翻译：场效应控制半导体元件
公开(公告)号：US06184555B2
公开(公告)日：2001-02-06
申请号：US09117636
申请日：1998-12-04
申请人： Jeno Tihanyi , Helmut Strack , Heinrich Geiger
发明人： Jeno Tihanyi , Helmut Strack , Heinrich Geiger
IPC分类号： H01L2976
CPC分类号： H01L29/7811 , H01L21/2257 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L29/7396 , H01L29/7802 , H01L29/7835
摘要： The invention relates to a field effect-controllable semiconductor component of vertical or lateral design i.e. MOSFETs and IGBTs. In this case, depletion zones and complementary depletion zones of opposite conduction types are introduced in the source-drain load path, in the semiconductor body, i.e. in the inner zone in the case of vertical components and in the drift zone in the case of lateral components, the concentration of the regions doped by the first conduction type corresponding approximately to the concentration of the regions doped by the second conduction type.
摘要翻译：本发明涉及垂直或侧向设计的场效应可控半导体元件，即MOSFET和IGBT。在这种情况下，相反导电类型的耗尽区和互补耗尽区被引入到半导体主体中的源极 - 漏极负载路径中，即在垂直分量的情况下在内部区域中，并且在横向由第一导电类型掺杂的区域的浓度大致对应于由第二导电类型掺杂的区域的浓度。

90. 发明授权

US5311052A Planar semiconductor component with stepped channel stopper electrode 失效
标题翻译：具有阶梯式通道阻挡电极的平面半导体元件
公开(公告)号：US5311052A
公开(公告)日：1994-05-10
申请号：US426783
申请日：1982-09-29
申请人： Jens P. Stengl , Helmut Strack , Jeno Tihanyi
发明人： Jens P. Stengl , Helmut Strack , Jeno Tihanyi
IPC分类号： H01L27/088 , H01L21/76 , H01L21/8234 , H01L27/06 , H01L27/22 , H01L29/06 , H01L29/40 , H01L29/78 , H01L29/861 , H01L29/34
CPC分类号： H01L29/404
摘要： Semiconductor component, including a semiconductor body having an edge, a surface, a substrate of a first given conductivity type, at least one zone being embedded in a planar manner in the substrate at the surface and being of a second conductivity type opposite the first given type, and insulating layer disposed on the surface, an electrode being in contact with the at least one zone, a channel stopper disposed on the insulating layer outside the at least one zone and in vicinity of the edge of the semiconductor body, the channel stopper being electrically connected to the substrate, and a field plate beind disposed on the insulating layer between the at least one zone and the channel stopper and being electrically connected to the at least one zone, the channel stopper being disposed at an increasing distance from the edge and the surface of the semiconductor body, as seen in direction toward the at least one zone.
摘要翻译：半导体部件，包括具有第一给定导电类型的边缘，表面，衬底的半导体本体，至少一个区域以平面方式嵌入在该表面的衬底中，并且具有与第一给定的相反的第二导电类型类型和绝缘层，与所述至少一个区域接触的电极，设置在所述至少一个区域外部并且位于所述半导体主体的边缘附近的所述绝缘层上的通道阻挡件，所述通道塞电连接到所述衬底，并且场板被设置在所述至少一个区域和所述通道阻挡件之间的所述绝缘层上并且电连接到所述至少一个区域，所述通道阻挡件设置在距所述边缘以及半导体本体的表面，从朝向至少一个区域的方向看。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式