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81. 发明申请

US20060054751A1 Vertically-adjustable mobile computer workstation and method of using same 审中-公开
标题翻译：垂直可调移动电脑工作站及其使用方法
公开(公告)号：US20060054751A1
公开(公告)日：2006-03-16
申请号：US10941231
申请日：2004-09-15
申请人： Brian Johnson , Gary Coonan
发明人： Brian Johnson , Gary Coonan
IPC分类号： A47F5/00
CPC分类号： F16M11/24 , A47B9/00 , F16M11/2021 , F16M11/2092 , F16M11/38 , F16M11/42 , F16M13/00 , F16M2200/024 , F16M2200/044 , F16M2200/063
摘要： Mobile computer workstations must be sufficiently large in order to be stable, but small enough to be easily maneuverable through a work place. A vertically-adjustable mobile computer workstation of the present disclosure includes a pole rotatably attached to a base supported by a plurality of rotatable members. The pole includes a first arm rotatably attached to a second arm. A computer support is attached to the second arm and is moveable between a sitting user position and a standing user position, at least in part, by pivoting the arms of the pole with respect to one another and the moveable base.
摘要翻译：移动计算机工作站必须足够大以便稳定，但足够小以便通过工作场所容易操纵。本公开的可垂直调节的移动计算机工作站包括可旋转地附接到由多个可旋转构件支撑的基座的杆。杆包括可旋转地附接到第二臂的第一臂。计算机支撑件附接到第二臂，并且可以在坐使用者位置和站立的使用者位置之间移动，至少部分地通过相对于彼此和可移动的基座枢转杆的臂。

82. 发明申请

US20050263590A1 Point of sale terminal having integrated customer and operator interfaces 审中-公开
标题翻译：销售点终端具有集成的客户和操作员界面
公开(公告)号：US20050263590A1
公开(公告)日：2005-12-01
申请号：US11049921
申请日：2005-02-03
申请人： James Branck , Brian Johnson
发明人： James Branck , Brian Johnson
IPC分类号： G06K15/00 , G07G1/00
CPC分类号： G07G1/0018
摘要： The present invention provides an integrated point of sale transaction terminal that includes both operator and customer interfaces. A housing for the electronics of the point of sale terminal comprises an operator interface unit integrally associated therewith and extending from one side thereof and a customer interface unit integrally associated therewith and extending from the opposing side thereof.
摘要翻译：本发明提供了包括操作者和客户界面的综合销售点交易终端。用于销售点终端的电子设备的壳体包括与其一体地相关联并从其一侧延伸的操作者接口单元和与其整体相关联并从其相对侧延伸的顾客接口单元。

83. 发明授权

US06965249B2 Programmable logic device with redundant circuitry 失效
标题翻译：具有冗余电路的可编程逻辑器件
公开(公告)号：US06965249B2
公开(公告)日：2005-11-15
申请号：US10159581
申请日：2002-05-30
申请人： Christopher Lane , Ketan Zaveri , Hyun Yi , Giles Powell , Paul Leventis , David Jefferson , David Lewis , Triet Nguyen , Vikram Santurkar , Michael Chan , Andy Lee , Brian Johnson , David Cashman
发明人： Christopher Lane , Ketan Zaveri , Hyun Yi , Giles Powell , Paul Leventis , David Jefferson , David Lewis , Triet Nguyen , Vikram Santurkar , Michael Chan , Andy Lee , Brian Johnson , David Cashman
IPC分类号： H01L21/82 , H03K19/177
CPC分类号： H03K19/17764 , H03K19/17736 , H03K19/17744
摘要： A programmable logic device and associated method is provided with repairable regions. In one aspect, general routing interconnect lines are segmented within repairable regions. In another aspect, IO bus lines and associated circuitry are provided that accommodate redundancy in a staggered segmented architecture. In another aspect, a dedicated routing architecture between particular logic regions accommodates shifting to define and utilize repairable regions. Principles of other aspects are illustrated and described in the context of several exemplary embodiments of aspects of the invention.
摘要翻译：可编程逻辑器件和相关方法提供有可修复区域。在一个方面，一般布线互连线在可修复区域内被分段。在另一方面，提供IO总线线路和相关电路，其适应交错分段结构中的冗余。在另一方面，特定逻辑区域之间的专用路由架构适应移位以限定和利用可修复区域。在本发明的方面的几个示例性实施例的上下文中示出和描述了其它方面的原理。

84. 发明申请

US20050063891A1 Method of producing carbon nanoparticles 审中-公开
标题翻译：生产碳纳米粒子的方法
公开(公告)号：US20050063891A1
公开(公告)日：2005-03-24
申请号：US10652554
申请日：2003-09-02
申请人： Milo Shaffer , Ian Kinloch , Alan Windle , Junfeng Geng , Brian Johnson , Charanjeet Singh , Ya-Li Li
发明人： Milo Shaffer , Ian Kinloch , Alan Windle , Junfeng Geng , Brian Johnson , Charanjeet Singh , Ya-Li Li
IPC分类号： C01B31/02 , D01F9/127 , D01F9/133 , D01F9/12
CPC分类号： B82Y30/00 , B82Y40/00 , C01B32/162 , C01B2202/02 , C01B2202/06 , D01F9/127 , D01F9/133
摘要： A method of producing carbon nanoparticles comprises the steps of: passing a gaseous carbon source through a heated reactor; and adding catalyst supported on substrate particles or thermally decomposable catalyst precursor supported on substrate particles to the heated reactor to form a fluidised bed; such that carbon nanoparticles are formed in the heated reactor.
摘要翻译：生产碳纳米颗粒的方法包括以下步骤：使气态碳源通过加热的反应器; 并将负载在基材颗粒上的催化剂或负载在基材颗粒上的可热分解的催化剂前体加入到加热的反应器中以形成流化床; 使得在加热的反应器中形成碳纳米颗粒。

85. 发明授权

US06857043B1 Shift register implementations of first-in/first-out memories utilizing a double increment gray code counter 有权
标题翻译：使用双增量灰度代码计数器的先进先出存储器的移位寄存器实现
公开(公告)号：US06857043B1
公开(公告)日：2005-02-15
申请号：US09761609
申请日：2001-01-16
申请人： Andy L. Lee , Brian Johnson , Richard G. Cliff
发明人： Andy L. Lee , Brian Johnson , Richard G. Cliff
IPC分类号： G06F5/10 , G06F5/14 , G06F12/00
CPC分类号： G06F5/14 , G06F2205/102
摘要： First-in/first-out (“FIFO”) memory circuitry includes first and second Gray-code-based counters for respectively counting write and read clock signals. A Gray code subtractor subtracts from one another the counts output by the counters. Shift register circuitry shifts in successive data words in synchronism with the write clock signal. The shift register circuitry includes selection circuitry configured to select one of the data words based on a Gray code decoding of information from the subtractor. Circuitry may also be included to monitor the information from the subtractor to detect full or empty conditions of the shift register circuitry.
摘要翻译：先进先出（“FIFO”）存储器电路包括用于分别计数写入和读取时钟信号的第一和第二基于格雷码的计数器。格雷码减法器从计数器输出的计数相减。移位寄存器电路与写时钟信号同步地移位连续的数据字。移位寄存器电路包括选择电路，其被配置为基于来自减法器的信息的格雷码解码来选择数据字之一。也可以包括电路以监视来自减法器的信息以检测移位寄存器电路的全部或空的条件。

86. 发明申请

US20050030800A1 Multilayered phase change memory 有权
标题翻译：多层相变存储器
公开(公告)号：US20050030800A1
公开(公告)日：2005-02-10
申请号：US10634130
申请日：2003-08-04
申请人： Brian Johnson , Stephen Hudgens
发明人： Brian Johnson , Stephen Hudgens
IPC分类号： G11C16/02 , H01L45/00 , G11C29/00
CPC分类号： G11C13/0004 , G11C2213/52 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/144
摘要： A phase change layer may switch between more and less conductive states in response to electrical stimulation. The phase change layer may be positioned over a non-switching ovonic material which acts as an electrode, a resistive heater, and an insulating barrier. The phase change layer may be positioned over a non-switching ovonic material which acts as an electrode, a resistive heater, and a thermal barrier.
摘要翻译：响应于电刺激，相变层可以在越来越少的导电状态之间切换。相变层可以位于用作电极，电阻加热器和绝缘屏障的非开关式超声波材料上。相变层可以位于作为电极，电阻加热器和热障壁的非切换式超声波材料上。

87. 发明申请

US20050007807A1 Apparatus and method for mounting microelectronic devices on a mirrored board assembly 有权
公开(公告)号：US20050007807A1
公开(公告)日：2005-01-13
申请号：US10910980
申请日：2004-08-03
申请人： Chris Martin , Brent Keeth , Brian Johnson , Walter Moden
发明人： Chris Martin , Brent Keeth , Brian Johnson , Walter Moden
IPC分类号： G11C5/00 , H05K1/18 , G11C7/00
CPC分类号： H05K1/181 , G11C5/04 , G11C5/06 , H05K1/112 , H05K2201/09409 , H05K2201/10159 , H05K2201/10545 , H05K2201/10689 , Y02P70/611
摘要： The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.

88. 发明授权

US06836166B2 Method and system for delay control in synchronization circuits 失效
标题翻译：同步电路延时控制方法与系统
公开(公告)号：US06836166B2
公开(公告)日：2004-12-28
申请号：US10339752
申请日：2003-01-08
申请人： Feng Lin , Brent Keeth , Brian Johnson
发明人： Feng Lin , Brent Keeth , Brian Johnson
IPC分类号： H03L706
CPC分类号： G11C7/222 , G11C7/1072 , H03L7/0814 , H03L7/0818 , H03L7/087
摘要： A synchronization circuit includes a first and second phase-shifting path circuit, with each generates a phase-shifted signal responsive to an input signal and the phase-shifted signal having respective fine and coarse phase shifts relative to the input signal. Each phase-shifting path circuit adjusts the coarse and fine phase shifts responsive to control signals. A selection circuit outputs one of the phase-shifted signals responsive to a selection signal. A control circuit monitors a phase shift between the input signal and the output phase-shifted signal and develops the selection and control signals to select one of the phase-shifting path circuits and to adjust the fine phase shift of the selected path circuit and the fine and coarse phase shifts of the other path circuit. When the fine delay of the selected phase-shifting path circuit has a threshold value, the control circuit develops the selection signal to select the other phase-shifting circuit.
摘要翻译：同步电路包括第一和第二移相路径电路，每个产生响应于输入信号的相移信号，并且相移信号相对于输入信号具有相应的精细和粗略的相移。每个移相路径电路响应于控制信号调整粗略和精细的相移。选择电路响应于选择信号输出一个相移信号。控制电路监视输入信号和输出相移信号之间的相移，并产生选择和控制信号以选择一个相移路径电路并调整所选路径电路的精细相移和精细和另一路径电路的粗相移。当所选择的移相路径电路的精细延迟具有阈值时，控制电路产生选择信号以选择另一个移相电路。

89. 发明授权

US06807500B2 Method and apparatus providing improved data path calibration for memory devices 失效
标题翻译：为存储器件提供改进的数据路径校准的方法和装置
公开(公告)号：US06807500B2
公开(公告)日：2004-10-19
申请号：US10292654
申请日：2002-11-13
申请人： Brian Johnson , Brent Keeth
发明人： Brian Johnson , Brent Keeth
IPC分类号： G06F112
CPC分类号： G11C29/028 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C29/02 , G11C29/50012 , G11C2207/2254
摘要： A method and apparatus for calibrating a data path of a digital circuit uses an even bit pseudo-random calibration pattern. A portion of the pattern is captured in a capture period and used to predict a next arriving portion of the calibration pattern. The next arriving portion of the calibration pattern is captured and then compared to the predicted pattern in a compare period, and the result of the comparison is used to relatively time data arriving in the data path to a clocking signal which clocks in the data. The time duration of the compare period may be varied to ensure that all possible bits of the calibration pattern are used in the calibration procedure.
摘要翻译：用于校准数字电路的数据路径的方法和装置使用偶数位伪随机校准模式。在捕获周期中捕获图案的一部分，并用于预测校准图案的下一个到达部分。捕获校准图案的下一个到达部分，然后在比较周期中与预测图案进行比较，并将比较结果用于到数据路径中的相对时间数据到数据中的时钟信号。可以改变比较周期的持续时间以确保在校准过程中使用校准图案的所有可能位。

90. 发明授权

US06751717B2 Method and apparatus for clock synchronization between a system clock and a burst data clock 失效
标题翻译：用于在系统时钟和突发数据时钟之间进行时钟同步的方法和装置
公开(公告)号：US06751717B2
公开(公告)日：2004-06-15
申请号：US09767490
申请日：2001-01-23
申请人： Brian Johnson
发明人： Brian Johnson
IPC分类号： G06F1200
CPC分类号： G06F13/28
摘要： The present invention coordinates the execution of commands, received in response to a continuous system clock, with the receipt of data in response to a burst clock. Command capture logic receives command information in response to the system clock. A storage element is responsive to the command capture logic for storing certain command information such as write commands. A two stage pipeline receives the command information from the storage element in response to the burst clock and outputs the command information in response to the system clock. Methods of operating the apparatus are also disclosed.
摘要翻译：本发明协调响应于连续系统时钟接收的响应于突发时钟的数据的接收的命令的执行。命令捕获逻辑响应系统时钟接收命令信息。存储元件响应于用于存储诸如写命令之类的某些命令信息的命令捕获逻辑。双级流水线响应于突发时钟从存储元件接收命令信息，并根据系统时钟输出命令信息。还公开了操作该装置的方法。

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