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81. 发明授权

US08932934B2 Methods of self-forming barrier integration with pore stuffed ULK material 有权
标题翻译：自制成形障碍与孔填充ULK材料的方法
公开(公告)号：US08932934B2
公开(公告)日：2015-01-13
申请号：US13903283
申请日：2013-05-28
申请人： GlobalFoundries Inc.
发明人： Moosung M. Chae , Errol Todd Ryan , Nicholas Vincent Licausi , Christian Witt , Ailian Zhao , Ming He , Sean X. Lin , Xunyuan Zhang , Kunaljeet Tanwar
IPC分类号： H01L21/76 , H01L21/768 , H01L23/48 , H01L21/316 , H01L21/02
CPC分类号： H01L21/76831 , H01L21/02203 , H01L21/3105 , H01L21/31695 , H01L21/7682 , H01L21/76843 , H01L2221/1047
摘要： A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench.
摘要翻译：提供了一种用于在半导体制造期间减少超低k层的自形成势垒的污染的方法的方法。一方面，一种方法包括：提供包含至少一个沟槽的固化的超低k膜，并且用孔填充材料填充膜的孔; 在沟槽的表面去除暴露的孔隙填充材料以形成暴露的孔; 并在沟槽的表面上形成自形成阻挡层。

82. 发明申请

US20140291847A1 METHODS OF FORMING A BARRIER SYSTEM CONTAINING AN ALLOY OF METALS INTRODUCED INTO THE BARRIER SYSTEM, AND AN INTEGRATED CIRCUIT PRODUCT CONTAINING SUCH A BARRIER SYSTEM 有权
标题翻译：形成包含金属合金进入障碍物系统的障碍物系统的方法以及包含这种障碍物系统的集成电路产品
公开(公告)号：US20140291847A1
公开(公告)日：2014-10-02
申请号：US13852084
申请日：2013-03-28
申请人： GLOBALFOUNDRIES INC.
发明人： Xunyuan Zhang , Hoon Kim , Vivian W. Ryan
IPC分类号： H01L21/768 , H01L23/532 , H01L23/522
CPC分类号： H01L23/5226 , H01L21/76846 , H01L21/76856 , H01L21/76858 , H01L21/76859 , H01L23/53214 , H01L23/53219 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53261 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier system comprised of at least one barrier material and at least two metallic elements, and performing a heating process to form a metal alloy comprised of the at least two metallic elements in the barrier system. Also disclosed is a device that comprises a trench/via in a layer of insulating material, a barrier system positioned in the trench/via, wherein the barrier system comprises at least one barrier material and a metal alloy comprised of at least two metallic elements that are comprised of materials other than the at least one barrier material, and a conductive structure positioned in the trench/via above the barrier system.
摘要翻译：本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，形成由至少一种阻挡材料和至少两种金属元素组成的阻挡系统，并且进行加热工艺以形成由屏障系统中至少有两个金属元素。还公开了一种装置，其包括绝缘材料层中的沟槽/通孔，位于沟槽/通孔中的阻挡系统，其中阻挡系统包括至少一种阻挡材料和由至少两个金属元素组成的金属合金，由至少一种阻挡材料以外的材料构成，以及位于屏障系统上方的沟槽/通孔中的导电结构。

83. 发明申请

US20140252617A1 BARRIER LAYER CONFORMALITY IN COPPER INTERCONNECTS 有权
标题翻译：铜箔互连中的阻隔层一致性
公开(公告)号：US20140252617A1
公开(公告)日：2014-09-11
申请号：US13786627
申请日：2013-03-06
申请人： GLOBALFOUNDRIES INC.
发明人： Errol Todd RYAN , Xunyuan Zhang
IPC分类号： H01L21/768 , H01L23/482
CPC分类号： H01L21/76843 , H01L21/76814 , H01L21/76826 , H01L2924/0002 , H01L2924/00
摘要： A process of modulating the thickness of a barrier layer deposited on the sidewalls and floor of a recessed feature in a semiconductor substrate is disclosed. The process includes altering the surface of the conductive feature on which the barrier layer is deposited by annealing in a reducing atmosphere and optionally additionally, silylating the dielectric surface that forms the sidewalls of the recessed feature.
摘要翻译：公开了一种调制沉积在半导体衬底中凹陷特征的侧壁和底板上的阻挡层的厚度的工艺。该方法包括通过在还原气氛中进行退火来改变其上沉积阻挡层的导电特征的表面，以及任选地另外地使形成凹陷特征的侧壁的电介质表面甲硅烷基化。

84. 发明申请

US20140252616A1 ELECTROLESS FILL OF TRENCH IN SEMICONDUCTOR STRUCTURE 有权
标题翻译：半导体结构中的电镀薄膜
公开(公告)号：US20140252616A1
公开(公告)日：2014-09-11
申请号：US13785934
申请日：2013-03-05
申请人： GLOBALFOUNDRIES INC.
发明人： Sean X. Lin , Xunyuan Zhang , Ming HE , Larry Zhao , John Iacoponi , Kunaljeet Tanwar
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76847 , H01L21/76843 , H01L21/76879 , H01L21/76882 , H01L23/48 , H01L2924/0002 , H01L2924/00
摘要： A trench in an inter-layer dielectric formed on a semiconductor substrate is defined by a bottom and sidewalls. A copper barrier lines the trench with a copper-growth-promoting liner over the barrier. The trench has bulk copper filling it, and includes voids in the copper. The copper with voids is removed, including from the sidewalls, leaving a void-free copper portion at the bottom. Immersion in an electroless copper bath promotes upward growth of copper on top of the void-free copper portion without inward sidewall copper growth, resulting in a void-free copper fill of the trench.
摘要翻译：在半导体衬底上形成的层间电介质中的沟槽由底部和侧壁限定。铜屏障通过屏障上的铜生长促进衬里将沟槽排列。沟槽有大量铜填充，并且在铜中包括空隙。具有空隙的铜被除去，包括从侧壁，在底部留下无空隙的铜部分。浸没在无电解铜浴中促进铜在无空隙铜部分顶部的向上生长，而不会向内侧壁铜生长，导致沟槽的无空隙铜填充。

85. 发明申请

US20140246775A1 METHODS OF FORMING NON-CONTINUOUS CONDUCTIVE LAYERS FOR CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT PRODUCT 有权
标题翻译：在集成电路产品上形成导电结构的非连续导电层的方法
公开(公告)号：US20140246775A1
公开(公告)日：2014-09-04
申请号：US13781921
申请日：2013-03-01
申请人： GLOBALFOUNDRIES INC.
发明人： Vivian W. Ryan , Xunyuan Zhang
IPC分类号： H01L21/768 , H01L23/498
CPC分类号： H01L21/76843 , H01L21/76846 , H01L21/76858 , H01L21/76868 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a non-continuous layer comprised of a plurality of spaced-apart conductive structures on the layer of insulating material in the trench/via, wherein portions of the layer of insulating material not covered by the plurality of spaced-apart conductive structures remain exposed, forming at least one barrier layer on the non-continuous layer, wherein the barrier layer contacts the spaced-apart conductive structures and the exposed portions of the layer of insulating material, forming at least one liner layer above the barrier layer, and forming a conductive structure in the trench/via above the liner layer.
摘要翻译：本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中的绝缘材料层上形成由多个间隔开的导电结构构成的非连续层，其中部分未被多个间隔开的导电结构覆盖的绝缘材料层保持暴露，在非连续层上形成至少一个阻挡层，其中阻挡层接触间隔开的导电结构和该层的暴露部分绝缘材料，在阻挡层上形成至少一个衬垫层，以及在衬里层上方的沟槽/通孔中形成导电结构。

86. 发明申请

US20140227872A1 METHODS OF FORMING CONDUCTIVE STRUCTURES USING A SACRIFICIAL LINER LAYER 有权
标题翻译：使用真空衬层形成导电结构的方法
公开(公告)号：US20140227872A1
公开(公告)日：2014-08-14
申请号：US13766898
申请日：2013-02-14
申请人： GLOBALFOUNDRIES INC.
发明人： Xunyuan Zhang , Nicholas V. LiCausi , Errol Todd Ryan
IPC分类号： H01L21/768
CPC分类号： H01L21/76807 , H01L2221/1063
摘要： One illustrative method disclosed herein includes performing a first etching process to define a via opening in a layer of insulating material, performing at least one process operation to form a sacrificial liner layer on the sidewalls of the via opening, performing a second etching process to define a trench in the layer of insulating material, wherein the sacrificial liner layer is exposed to the second etching process, after performing the second etching process, performing a third etching process to remove the sacrificial liner layer and, after performing the third etching process, forming a conductive structure in at least the via opening and the trench.
摘要翻译：本文公开的一种说明性方法包括执行第一蚀刻工艺以在绝缘材料层中限定通孔开口，执行至少一个工艺操作以在通孔开口的侧壁上形成牺牲衬垫层，执行第二蚀刻工艺以界定在所述绝缘材料层中的沟槽，其中所述牺牲衬垫层在进行所述第二蚀刻工艺之后暴露于所述第二蚀刻工艺，执行第三蚀刻工艺以去除所述牺牲衬垫层，并且在执行所述第三蚀刻工艺之后，形成至少在通孔开口和沟槽中的导电结构。

87. 发明授权

US08623758B1 Subtractive metal multi-layer barrier layer for interconnect structure 有权
标题翻译：用于互连结构的减金属多层势垒层
公开(公告)号：US08623758B1
公开(公告)日：2014-01-07
申请号：US13657182
申请日：2012-10-22
申请人： GLOBALFOUNDRIES Inc.
发明人： Vivian W. Ryan , Xunyuan Zhang , Paul R. Besser
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76852 , H01L21/76858 , H01L2221/1078 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A method includes forming an adhesion barrier layer over a dielectric layer formed on a substrate. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. A metal layer is formed over the stress-reducing barrier layer. The metal layer, adhesion barrier layer, and stress-reducing barrier layer define an interconnect metal stack. Recesses are defined in the interconnect metal stack to expose the dielectric layer. The recesses are filled with a dielectric material, wherein a portion of the interconnect metal stack disposed between adjacent recessed filled with dielectric material defines an interconnect structure.
摘要翻译：一种方法包括在形成在基底上的电介质层上形成粘合阻挡层。第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。在粘合阻挡层上方形成有应力降低阻挡层。所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。在应力降低阻挡层上形成金属层。金属层，粘合阻挡层和应力减小阻挡层限定互连金属叠层。在互连金属叠层中限定凹陷以暴露电介质层。这些凹部填充有电介质材料，其中设置在相邻凹陷的填充有电介质材料的互连金属叠层的一部分限定互连结构。

88. 发明授权

US10679937B2 Devices and methods of forming low resistivity noble metal interconnect 有权
公开(公告)号：US10679937B2
公开(公告)日：2020-06-09
申请号：US15785665
申请日：2017-10-17
申请人： GLOBALFOUNDRIES Inc.
发明人： Xunyuan Zhang , Frank W. Mont , Errol Todd Ryan
IPC分类号： H01L23/522 , H01L23/532 , H01L21/02 , H01L21/285 , H01L21/768 , H01L23/528
摘要： Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

89. 发明授权

US10485111B2 Via and skip via structures 有权
公开(公告)号：US10485111B2
公开(公告)日：2019-11-19
申请号：US15647400
申请日：2017-07-12
申请人： GLOBALFOUNDRIES INC.
发明人： Shao Beng Law , Nicholas V. LiCausi , Errol Todd Ryan , James McMahon , Ryan S. Smith , Xunyuan Zhang
IPC分类号： H05K3/46 , H05K3/40 , H05K1/11 , H01L21/768
摘要： The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.

90. 发明申请

US20190318927A1 METHODS OF PROTECTING STRUCTURE OF INTEGRATED CIRCUIT FROM REWORK 审中-公开
公开(公告)号：US20190318927A1
公开(公告)日：2019-10-17
申请号：US15954066
申请日：2018-04-16
申请人： GLOBALFOUNDRIES INC.
发明人： Lei Sun , Xunyuan Zhang , Frank W. Mont , Shao Beng Law
IPC分类号： H01L21/033 , H01L21/768 , H01L21/027 , H01L21/02
摘要： The present disclosure relates to methods of protecting a structure of an integrated circuit (IC) from rework, and more particularly, to methods of protecting a structure of an IC without impacting the critical dimension or the profile of the structure. For example, a method of protecting a structure of an IC from rework may include forming a first layer on a second layer; forming one or more first openings in the first layer, the first openings exposing a top surface of the second layer; selectively growing a Group VIII metal within the one or more first openings, thereby forming one or more first plugs; forming one or more final openings in the first layer; and removing the one or more first plugs.

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