专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US06337506B2 Semiconductor memory device capable of performing stable operation for noise while preventing increase in chip area 失效
标题翻译：半导体存储器件能够在防止芯片面积增加的同时对噪声进行稳定的操作
公开(公告)号：US06337506B2
公开(公告)日：2002-01-08
申请号：US09116887
申请日：1998-07-16
申请人： Fukashi Morishita , Teruhiko Amano , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Takahiro Tsuruda , Mitsuya Kinoshita , Mako Kobayashi
发明人： Fukashi Morishita , Teruhiko Amano , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Takahiro Tsuruda , Mitsuya Kinoshita , Mako Kobayashi
IPC分类号： H01L2900
CPC分类号： H01L23/552 , G11C5/14 , H01L21/761 , H01L23/585 , H01L27/0203 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： A power supply circuit and an oscillation circuit or the like of noise generation sources are concentrated, and the periphery thereof is surrounded by a guard ring. Guard ring is provided to have bonding pads at least partially thereon. Guard ring is effectively provided utilizing the region below bonding pads, so that effective noise reduction is achieved while preventing increase in chip area.
摘要翻译：噪声产生源的电源电路和振荡电路等被集中，其周边被保护环包围。提供保护环以至少部分地具有接合焊盘。利用焊盘下方的区域有效地提供保护环，从而在防止芯片面积的增加的同时实现有效的降噪。

82. 发明授权

US06184744B2 Internal power supply voltage generation circuit that can suppress reduction in internal power supply voltage in neighborhood of lower limit region of external power supply voltage 失效
公开(公告)号：US06184744B2
公开(公告)日：2001-02-06
申请号：US09149079
申请日：1998-09-08
申请人： Fukashi Morishita
发明人： Fukashi Morishita
IPC分类号： G05F110
CPC分类号： G05F1/465
摘要： An internal power supply voltage generation circuit includes a main amplifier that supplies a current from an external power supply node to an internal power supply line in accordance with the difference between a reference voltage from a reference voltage generation circuit and an internal power supply voltage on the internal power supply line. The current supply amount by the main amplifier is adjusted by a level adjust circuit, according to the difference between the external power supply voltage and the reference voltage. The internal power supply voltage generation circuit can suppress reduction in the internal power supply voltage in the vicinity of the lower limit area of the differential power supply voltage.

83. 发明授权

US6046476A SOI input protection circuit 失效
标题翻译： SOI输入保护电路
公开(公告)号：US6046476A
公开(公告)日：2000-04-04
申请号：US559264
申请日：1995-11-15
申请人： Fukashi Morishita , Kazutami Arimoto
发明人： Fukashi Morishita , Kazutami Arimoto
IPC分类号： H01L21/28 , H01L21/02 , H01L21/762 , H01L27/02 , H01L27/06 , H01L27/12 , H01L29/861 , H01L29/866
CPC分类号： H01L27/0251 , H01L27/1203 , H01L2924/0002
摘要： In an input protection circuit having an SOI structure for protecting a MOSFET against breaking caused by a high voltage such as static electricity, a trench is provided in an SOI substrate to vertically pass through a silicon layer and a buried oxide film and reach the interior of a P-type silicon substrate. An n.sup.+ polysilicon layer is buried in the trench, to be connected with the silicon substrate by a P-N junction. A wire is connected to the n.sup.+ polysilicon layer. An end of the wire is connected to an input pad, and another end thereof is connected to an internal circuit. An input voltage is limited by an avalanche breakdown at the P-N junction in the interface between the n.sup.+ polysilicon layer and the P-type silicon substrate.
摘要翻译：在具有SOI结构的输入保护电路中，用于保护MOSFET免受诸如静电的高电压引起的断开，在SOI衬底中提供沟槽以垂直地穿过硅层和掩埋氧化物膜并到达内部 P型硅衬底。 n +多晶硅层埋在沟槽中，通过P-N结与硅衬底连接。导线连接到n +多晶硅层。电线的一端连接到输入焊盘，另一端连接到内部电路。输入电压受到在n +多晶硅层和P型硅衬底之间的界面处的P-N结处的雪崩击穿的限制。

84. 发明授权

US5841172A SOI input protection circuit 失效
公开(公告)号：US5841172A
公开(公告)日：1998-11-24
申请号：US833200
申请日：1997-04-14
申请人： Fukashi Morishita , Kazutami Arimoto
发明人： Fukashi Morishita , Kazutami Arimoto
IPC分类号： H01L21/28 , H01L21/02 , H01L21/762 , H01L27/02 , H01L27/06 , H01L27/12 , H01L29/861 , H01L29/866 , H01L23/62
CPC分类号： H01L27/0251 , H01L27/1203 , H01L2924/0002
摘要： In an input protection circuit having an SOI structure for protecting a MOSFET against breaking caused by a high voltage such as static electricity, a trench is provided in an SOI substrate to vertically pass through a silicon layer and a buried oxide film and reach the interior of a P-type silicon substrate. An n.sup.+ polysilicon layer is buried in the trench, to be connected with the silicon substrate by a P-N junction. A wire is connected to the n.sup.+ polysilicon layer. An end of the wire is connected to an input pad, and another end thereof is connected to an internal circuit. An input voltage is limited by an avalanche breakdown at the P-N junction in the interface between the n.sup.+ polysilicon layer and the P-type silicon substrate.

85. 发明授权

US08310852B2 Content addressable memory 有权
公开(公告)号：US08310852B2
公开(公告)日：2012-11-13
申请号：US13419217
申请日：2012-03-13
申请人： Naoya Watanabe , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
发明人： Naoya Watanabe , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
IPC分类号： G11C15/00 , G11C15/04 , G11C7/14 , G11C7/06 , G11C7/12 , G11C7/22
CPC分类号： G11C15/043 , G11C7/06 , G11C7/12 , G11C7/14 , G11C7/22 , G11C15/04 , G11C15/046
摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

86. 发明授权

US08014224B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08014224B2
公开(公告)日：2011-09-06
申请号：US12201024
申请日：2008-08-29
申请人： Kenji Yoshinaga , Fukashi Morishita
发明人： Kenji Yoshinaga , Fukashi Morishita
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by an internal buck voltage. On the other hand, a data path with high power consumption is driven by an external power supply voltage. A level conversion circuit receives an address signal or a command signal having a voltage level of the external power supply voltage, converts the voltage level to the internal buck voltage, and outputs a resultant signal to the control circuit. A level conversion circuit receives a control signal having a voltage level of the internal buck voltage from the control circuit, converts the voltage level to the external power supply voltage, and outputs a resultant signal to the data path.
摘要翻译：提供了由内部发电电路产生的内部电力提供的半导体器件，以执行稳定的操作，并且还抑制功耗。控制电路，行/列解码器和读出放大器由内部降压电压驱动。另一方面，具有高功耗的数据路径由外部电源电压驱动。电平转换电路接收具有外部电源电压的电压电平的地址信号或指令信号，将电压电平转换为内部降压电压，并将结果信号输出到控制电路。电平转换电路从控制电路接收具有内部降压电压的电压电平的控制信号，将电压电平转换为外部电源电压，并将结果信号输出到数据路径。

87. 发明申请

US20110182131A1 SEMICONDUCTOR DEVICE INCLUDING INTERNAL VOLTAGE GENERATION CIRCUIT 失效
标题翻译：包括内部电压发生电路的半导体器件
公开(公告)号：US20110182131A1
公开(公告)日：2011-07-28
申请号：US13080114
申请日：2011-04-05
申请人： Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
发明人： Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
IPC分类号： G11C5/14
CPC分类号： G05F1/468 , G11C5/025 , G11C5/147
摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
摘要翻译：半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。因此，相对于负电压的变化的响应增加。在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路活性。因此，可以防止待机电流的增加。

88. 发明申请

US20100231768A1 SOLID-STATE IMAGE PICKUP DEVICE 有权
标题翻译：固态图像拾取器件
公开(公告)号：US20100231768A1
公开(公告)日：2010-09-16
申请号：US12722121
申请日：2010-03-11
申请人： Hiroto Utsunomiya , Katsumi Dosaka , Hiroshi Kato , Fukashi Morishita , Fumiyasu Sasaki
发明人： Hiroto Utsunomiya , Katsumi Dosaka , Hiroshi Kato , Fukashi Morishita , Fumiyasu Sasaki
IPC分类号： H04N5/335
CPC分类号： H04N5/37455 , H03M1/1205 , H03M1/144 , H03M1/403 , H03M1/66 , H03M2201/16 , H04N5/374 , H04N5/3742 , H04N5/3765 , H04N5/378
摘要： There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.
摘要翻译：提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。通过垂直读出线输出的像素信号的电位被保持在节点处。多个电容器电容耦合到保持像素信号的节点。通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。此后，开始数字值的低位的转换。因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。

89. 发明申请

US20100188120A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
标题翻译：半导体集成电路设备
公开(公告)号：US20100188120A1
公开(公告)日：2010-07-29
申请号：US12677745
申请日：2008-09-19
申请人： Fukashi Morishita
发明人： Fukashi Morishita
IPC分类号： H03K19/0944
CPC分类号： H01L27/1203 , H01L27/088 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L29/7841 , H01L29/78615
摘要： The present invention provides a semiconductor integrated circuit device in which characteristics of an SOI transistor are effectively used to achieve higher speed, higher degree of integration, and also reduction in voltage and power consumption. The semiconductor integrated circuit device according to the present invention has a configuration in which a plurality of external power supply lines and body voltage control lines are alternately arranged in one direction so as to extend over the entire chip, which supply power and a body voltage to logic circuits, an analog circuit and memory circuits. A body voltage control type logic gate is fully applied in the logic circuit, whereas the body voltage control type logic gate is partially applied in the memory circuit.
摘要翻译：本发明提供一种半导体集成电路器件，其中SOI晶体管的特性被有效地用于实现更高的速度，更高的集成度，并且还降低了电压和功耗。根据本发明的半导体集成电路器件具有这样的结构，其中多个外部电源线和体电压控制线在一个方向上交替布置，以便在整个芯片上延伸，从而将电源和体电压提供给逻辑电路，模拟电路和存储器电路。体电压控制型逻辑门完全应用在逻辑电路中，而体电压控制型逻辑门部分地应用于存储器电路中。

90. 发明授权

US07498207B2 Semiconductor memory device and manufacturing method of the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07498207B2
公开(公告)日：2009-03-03
申请号：US11902996
申请日：2007-09-27
申请人： Masakazu Hirose , Fukashi Morishita
发明人： Masakazu Hirose , Fukashi Morishita
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L27/10873 , G11C11/404 , G11C11/4085 , G11C2211/4016 , H01L21/84 , H01L27/0218 , H01L27/10808 , H01L27/10817 , H01L27/10832 , H01L27/10835 , H01L27/10882 , H01L27/10894 , H01L27/1203 , H01L29/78612
摘要： In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.
摘要翻译：在该半导体存储器件中，在绝缘层中设置不形成有绝缘层的电位钳位区域。更具体地，电位钳位区域形成在靠近第一杂质区域的位置的主体部分下方，并延伸到第一半导体层。主体固定部分形成在主体部分和电位夹紧区域之间的边界区域中。在SOI（绝缘体上硅）结构中形成DRAM单元的情况下，这种结构能够提高操作性能而不增加布局面积。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式