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81. 发明授权

US07288451B2 Method and structure for forming self-aligned, dual stress liner for CMOS devices 失效
标题翻译：用于形成CMOS器件自对准双应力衬垫的方法和结构
公开(公告)号：US07288451B2
公开(公告)日：2007-10-30
申请号：US10906669
申请日：2005-03-01
申请人： Huilong Zhu , Huicai Zhong , Effendi Leobandung
发明人： Huilong Zhu , Huicai Zhong , Effendi Leobandung
IPC分类号： H01L21/8238
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823828 , H01L29/6653 , H01L29/7843 , Y10S438/938
摘要： A method for forming a self-aligned, dual stress liner for a CMOS device includes forming a first type stress layer over a first polarity type device and a second polarity type device, and forming a sacrificial layer over the first type nitride layer. Portions of the first type stress layer and the sacrificial layer over the second polarity type device are patterned and removed. A second type stress layer is formed over the second polarity type device, and over remaining portions of the sacrificial layer over the first polarity type device in a manner such that the second type stress layer is formed at a greater thickness over horizontal surfaces than over sidewall surfaces. Portions of the second type stress liner on sidewall surfaces are removed, and portions of the second type stress liner over the first polarity type device are removed.
摘要翻译：用于形成用于CMOS器件的自对准双应力衬垫的方法包括在第一极性类型器件和第二极性器件上形成第一类型应力层，并在第一氮化物层上形成牺牲层。第一类型应力层和第二极性类型器件上的牺牲层的部分被图案化和去除。第二类型应力层形成在第二极性类型器件上方，并且在第一极性类型器件上方的牺牲层的剩余部分上，以使得第二类型应力层在水平表面上比在侧壁上形成更大的厚度表面。除去侧壁表面上的第二类型应力衬垫的部分，并且去除第一极性类型装置上的第二类型应力衬垫的部分。

82. 发明申请

US20060199326A1 METHOD AND STRUCTURE FOR FORMING SELF-ALIGNED, DUAL STRESS LINER FOR CMOS DEVICES 失效
标题翻译：用于形成用于CMOS器件的自对准双重应力衬垫的方法和结构
公开(公告)号：US20060199326A1
公开(公告)日：2006-09-07
申请号：US10906669
申请日：2005-03-01
申请人： Huilong Zhu , Huicai Zhong , Effendi Leobandung
发明人： Huilong Zhu , Huicai Zhong , Effendi Leobandung
IPC分类号： H01L21/8238
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823828 , H01L29/6653 , H01L29/7843 , Y10S438/938
摘要： A method for forming a self-aligned, dual stress liner for a CMOS device includes forming a first type stress layer over a first polarity type device and a second polarity type device, and forming a sacrificial layer over the first type nitride layer. Portions of the first type stress layer and the sacrificial layer over the second polarity type device are patterned and removed. A second type stress layer is formed over the second polarity type device, and over remaining portions of the sacrificial layer over the first polarity type device in a manner such that the second type stress layer is formed at a greater thickness over horizontal surfaces than over sidewall surfaces. Portions of the second type stress liner on sidewall surfaces are removed, and portions of the second type stress liner over the
摘要翻译：用于形成用于CMOS器件的自对准双应力衬垫的方法包括在第一极性类型器件和第二极性器件上形成第一类型应力层，并在第一氮化物层上形成牺牲层。第一类型应力层和第二极性类型器件上的牺牲层的部分被图案化和去除。第二类型应力层形成在第二极性类型器件上方，并且在第一极性类型器件上方的牺牲层的剩余部分上，以使得第二类型应力层在水平表面上比在侧壁上形成更大的厚度表面。去除侧壁表面上的第二类应力衬垫的部分，并且将第二类型应力衬垫的部分移出

83. 发明申请

US20060151787A1 LOW CONCENTRATION SiGe BUFFER DURING STRAINED Si GROWTH OF SSGOI MATERIAL FOR DOPANT DIFFUSION CONTROL AND DEFECT REDUCTION 审中-公开
标题翻译：低浓度SiGe缓冲器在应变Si生长的SSGOI材料的痰液扩散控制和缺陷减少
公开(公告)号：US20060151787A1
公开(公告)日：2006-07-13
申请号：US10905595
申请日：2005-01-12
申请人： Huajie Chen , Anda Mocuta , Stephen Bedell , Effendi Leobandung , Devendra Sadana
发明人： Huajie Chen , Anda Mocuta , Stephen Bedell , Effendi Leobandung , Devendra Sadana
IPC分类号： H01L29/12 , H01L21/20
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/0251 , H01L21/02532
摘要： A method and structure for fabricating a strained semiconductor on a relaxed SiGe substrate which has dopant diffusion control and defect reduction are provided. Specifically, the dopant diffusion control and defect reduction is achieved in the present invention by providing a SiGe buffer layer between the strained semiconductor and the underlying relaxed SiGe substrate. In accordance with the present invention, the SiGe buffer layer has a Ge content that is less than the Ge content which is present in the relaxed SiGe substrate.
摘要翻译：提供了在具有掺杂剂扩散控制和缺陷减少的松弛SiGe衬底上制造应变半导体的方法和结构。具体地，通过在应变半导体和下面的弛豫SiGe衬底之间提供SiGe缓冲层，在本发明中实现了掺杂剂扩散控制和缺陷减少。根据本发明，SiGe缓冲层的Ge含量小于弛豫SiGe衬底中存在的Ge含量。

84. 发明授权

US06437400B1 Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall 有权
公开(公告)号：US06437400B1
公开(公告)日：2002-08-20
申请号：US09837136
申请日：2001-04-18
申请人： Effendi Leobandung
发明人： Effendi Leobandung
IPC分类号： H01L2976
摘要： A process for fabricating a tapered trench on a silicon substrate. The process comprises the steps of forming an initial trench in the substrate and implanting nitrogen ions on the initial trench side walls. More nitrogen ions are implanted adjacent the exposed surface of the substrate than adjacent the trench bottom. Finally, the initial trench side walls are oxidized to create the tapered shape.

85. 发明授权

US6069380A Single-electron floating-gate MOS memory 失效
标题翻译：单电子浮栅MOS存储器
公开(公告)号：US6069380A
公开(公告)日：2000-05-30
申请号：US900947
申请日：1997-07-25
申请人： Stephen Y. Chou , Lingjie Guo , Effendi Leobandung
发明人： Stephen Y. Chou , Lingjie Guo , Effendi Leobandung
IPC分类号： H01L29/788
CPC分类号： B82Y10/00 , H01L29/7888 , Y10S977/937
摘要： A Single Electron MOS Memory (SEMM), in which one bit of information is represented by storing only one electron, has been demonstrated at room temperature. The SEMM is a floating gate Metal-Oxide-Semiconductor (MOS) transistor in silicon with a channel width (about 10 nanometers) which is smaller than the Debye screening length of a single electron stored on the floating gate, and a nanoscale polysilicon dot (about 7 nanometers by 7 nanometers by 2 nanometers) as the floating gate which is positioned between the channel and the control gate. An electron stored on the floating gate can screen the entire channel from the potential on the control gate, and lead to: (i) a discrete shift in the threshold voltage; (ii) a staircase relation between the charging voltage and the shift; and (iii) a self-limiting charging process. The structure and fabrication of the SEMM is well adapted to the manufacture of ultra large-scale integrated circuits.
摘要翻译：已经在室温下证明了单电子MOS存储器（SEMM），其中一位信息仅通过仅存储一个电子来表示。 SEMM是硅中的浮栅金属氧化物半导体（MOS）晶体管，其通道宽度（约10纳米）小于存储在浮置栅极上的单个电子的德拜屏蔽长度，以及纳米级多晶硅点（约7纳米×7纳米×2纳米）作为位于通道和控制门之间的浮动栅极。存储在浮置栅极上的电子可以从控制栅极上的电位屏蔽整个通道，并导致：（i）阈值电压的离散移位; （ii）充电电压与偏移之间的阶梯关系; 和（iii）自限制充电过程。 SEMM的结构和制造适应于超大规模集成电路的制造。

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