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81. 发明授权

US08954779B2 Method for checking signal and module activities in a timer module and timer module 有权
标题翻译：在定时器模块和定时器模块中检查信号和模块活动的方法
公开(公告)号：US08954779B2
公开(公告)日：2015-02-10
申请号：US13637137
申请日：2011-03-16
申请人： Eberhard Boehl
发明人： Eberhard Boehl
IPC分类号： G06F1/14 , G06F11/07 , G06F11/30
CPC分类号： G06F11/0739 , G06F11/0757 , G06F11/3013 , G06F11/3055
摘要： A timer module having a status register is connectable to an external arithmetic unit and generates at least one activity signal for an internal signal of the timer module and/or an internal unit of the timer module and/or a process within the internal unit, and enters an activity status into a status register in the event of a determined activity, and allows the activity status to be polled and reset by the external arithmetic unit at times determined by the external arithmetic unit. Furthermore, the activity status entered into the status register remains until it is reset by the external arithmetic unit.
摘要翻译：具有状态寄存器的定时器模块可连接到外部算术单元，并且为定时器模块的内部信号和/或定时器模块的内部单元和/或内部单元内的处理生成至少一个活动信号，以及在确定的活动的情况下，将活动状态输入状态寄存器，并允许外部算术单元在由外部算术单元确定的时间轮询和复位活动状态。此外，进入状态寄存器的活动状态保持不变，直到外部算术单元复位为止。

82. 发明授权

US08910181B2 Divided central data processing 有权
标题翻译：分割中央数据处理
公开(公告)号：US08910181B2
公开(公告)日：2014-12-09
申请号：US13637843
申请日：2011-03-17
申请人： Eberhard Boehl , Ruben Bartholomae
发明人： Eberhard Boehl , Ruben Bartholomae
IPC分类号： G06F9/48 , G06F9/50 , G06F9/38
CPC分类号： G06F9/5083 , G06F9/4881
摘要： A circuit configuration for a data processing system and a corresponding method for executing multiple tasks by way of a central processing unit having a processing capacity assigned to the processing unit, the circuit configuration being configured to distribute the processing capacity of the processing unit uniformly among the respective tasks, and to process the respective tasks in time-offset fashion until they are respectively executed.
摘要翻译：一种用于数据处理系统的电路配置和用于通过具有分配给处理单元的处理能力的中央处理单元执行多个任务的相应方法，该电路配置被配置为将处理单元的处理能力在各自的任务，并且以时间偏移方式处理相应的任务，直到它们被分别执行。

83. 发明申请

US20140219444A1 Method for Generating a Random Output Bit Sequence 有权
标题翻译：生成随机输出位序列的方法
公开(公告)号：US20140219444A1
公开(公告)日：2014-08-07
申请号：US14131134
申请日：2012-06-19
申请人： Eberhard Boehl , Paulius Duplys
发明人： Eberhard Boehl , Paulius Duplys
IPC分类号： H04L9/08
CPC分类号： H04L9/0816 , G06F7/582 , H04L9/003 , H04L9/004 , H04L2209/24
摘要： A method and a random bit generator for generating a random output bit sequence. In this method, a configuration of 2n state machines is used, the state machines each including n state bits, each state machine always assuming a different state than the other state machines of the configuration, an input signal being supplied to the input end of the state machines, and these each generating n signature bits, which together form a signature bit sequence, as a function of their state, the random output bit sequence being generated by selection of individual bits from the signature bit sequences of all state machines of the configuration.
摘要翻译：一种用于产生随机输出位序列的方法和随机位产生器。在该方法中，使用2n状态机的结构，每个包括n个状态位的状态机，每个状态机总是假定与该配置的其他状态机不同的状态，输入信号被提供给状态机，并且它们每个生成n个签名比特，它们一起形成签名比特序列，作为其状态的函数，通过从配置的所有状态机的签名比特序列中选择各个比特来生成随机输出比特序列。

84. 发明授权

US08499113B2 Circuit configurations and method for controlling a data exchange in a circuit configuration 有权
标题翻译：用于控制电路配置中的数据交换的电路配置和方法
公开(公告)号：US08499113B2
公开(公告)日：2013-07-30
申请号：US13138607
申请日：2010-02-24
申请人： Eberhard Boehl , Ruben Bartholomae , Uwe Scheurer
发明人： Eberhard Boehl , Ruben Bartholomae , Uwe Scheurer
IPC分类号： G06F13/00
CPC分类号： G06F13/362
摘要： In a method for controlling a data exchange between at least one set of data sinks and at least one set of data sources in circuit configurations and circuit sequences, which circuit configurations have at least one arbitration unit, the arbitration unit selects a first data sink (data sink arbitration) and a first data source (data source arbitration) according to a predefined sequence, and outputs an address of a first data source and a request signal and an address of a first data sink and a validity signal. Data of the first data source are stored in the first data sink.
摘要翻译：在一种用于控制至少一组数据宿和电路配置和电路序列中的至少一组数据源之间的数据交换的方法中，哪些电路配置具有至少一个仲裁单元，仲裁单元选择第一数据宿（数据宿仲裁）和第一数据源（数据源仲裁），并且输出第一数据源和请求信号的地址以及第一数据宿的地址和有效信号。第一数据源的数据被存储在第一数据接收器中。

85. 发明申请

US20130080104A1 METHOD FOR SYSTEMATICALLY TREATING ERRORS 有权
标题翻译：用于系统处理错误的方法
公开(公告)号：US20130080104A1
公开(公告)日：2013-03-28
申请号：US13637753
申请日：2011-03-16
申请人： Eberhard Boehl , Bernd Becker , Bernard Pawlok
发明人： Eberhard Boehl , Bernd Becker , Bernard Pawlok
IPC分类号： G06F17/00
CPC分类号： G06F17/00 , G01D5/24452 , G01D5/24471 , G01D5/2449 , G01D5/2457
摘要： A method for systematically handling errors, and an assemblage for carrying out the method, are presented. The method serves for systematically handing errors for a goniometer in the context of the transfer of position data with a position transducer, the position transducer possessing markings that are sensed with at least one sensor; a profile being deposited in a memory region in connection with said markings; the position transducer generating as a function of its position, by way of the markings, position signals that carry, as data, parameters that are deposited into a further memory region beginning with an address pointer value of 0; said address pointer being incremented with each position signal; and a synchronization between the position signals and the profile being created, and the values stored in the profile being used to modify the number of pulses outputted to the goniometer.
摘要翻译：提出了系统地处理错误的方法，以及用于执行该方法的组合。该方法用于在用位置传感器传送位置数据的上下文中系统地处理测角器的误差，位置传感器具有用至少一个传感器感测的标记; 轮廓被沉积在与所述标记相关联的存储区域中; 位置传感器通过标记产生作为其位置的函数的位置信号，作为数据，载入从地址指针值0开始的另外的存储区域中的参数的位置信号; 所述地址指针随每个位置信号递增; 以及位置信号和所创建的轮廓之间的同步，并且存储在轮廓中的值用于修改输出到测角器的脉冲数。

86. 发明申请

US20130073891A1 METHOD FOR CHECKING SIGNAL AND MODULE ACTIVITIES IN A TIMER MODULE AND TIMER MODULE 有权
标题翻译：在定时器模块和定时器模块中检查信号和模块活动的方法
公开(公告)号：US20130073891A1
公开(公告)日：2013-03-21
申请号：US13637137
申请日：2011-03-16
申请人： Eberhard Boehl
发明人： Eberhard Boehl
IPC分类号： G06F1/14
CPC分类号： G06F11/0739 , G06F11/0757 , G06F11/3013 , G06F11/3055
摘要： A timer module having a status register is connectable to an external arithmetic unit and generates at least one activity signal for an internal signal of the timer module and/or an internal unit of the timer module and/or a process within the internal unit, and enters an activity status into a status register in the event of a determined activity, and allows the activity status to be polled and reset by the external arithmetic unit at times determined by the external arithmetic unit. Furthermore, the activity status entered into the status register remains until it is reset by the, external arithmetic unit.
摘要翻译：具有状态寄存器的定时器模块可连接到外部算术单元，并且为定时器模块的内部信号和/或定时器模块的内部单元和/或内部单元内的处理生成至少一个活动信号，以及在确定的活动的情况下，将活动状态输入状态寄存器，并允许外部算术单元在由外部算术单元确定的时间轮询和复位活动状态。此外，进入状态寄存器的活动状态保持不变，直到由外部运算单元复位。

87. 发明申请

US20130073256A1 TIMER MODULE AND METHOD FOR TESTING OUTPUT SIGNALS OF A TIMER MODULE 有权
标题翻译：定时器模块和测试定时器模块输出信号的方法
公开(公告)号：US20130073256A1
公开(公告)日：2013-03-21
申请号：US13637130
申请日：2011-03-17
申请人： Eberhard Boehl , Stephen Schmitt , Juergen Hanisch
发明人： Eberhard Boehl , Stephen Schmitt , Juergen Hanisch
IPC分类号： G04F10/00 , G06F15/00
CPC分类号： G06F11/1604 , G06F1/04 , G06F11/1608 , G06F11/1679
摘要： In a timer module having at least two output channels, the at least two output channels are configurable in such a way that they generate redundant output signals, and the generation of the redundant output signals begins synchronously. In addition, the timer module has provides a comparison of the redundant output signals by an EXOR logic operation and stores a result of the EXOR logic operation in a way that allows the result to be retained for an erroneous comparison until it is reset by an access.
摘要翻译：在具有至少两个输出通道的定时器模块中，所述至少两个输出通道可以以这样的方式配置，使得它们产生冗余输出信号，并且冗余输出信号的产生同步开始。此外，定时器模块通过EXOR逻辑运算提供了冗余输出信号的比较，并且以允许结果被保留以进行错误比较的方式存储EXOR逻辑运算的结果，直到其被访问重置为止。

88. 发明授权

US08219796B2 Method and device for controlling a computer system 有权
标题翻译：用于控制计算机系统的方法和装置
公开(公告)号：US08219796B2
公开(公告)日：2012-07-10
申请号：US12063250
申请日：2006-07-26
申请人： Reinhard Weiberle , Bernd Mueller , Eberhard Boehl , Yorck von Collani , Rainer Gmehlich
发明人： Reinhard Weiberle , Bernd Mueller , Eberhard Boehl , Yorck von Collani , Rainer Gmehlich
IPC分类号： G06F9/00 , G06F1/04 , G06F15/16 , G06F15/167 , G06F12/00 , G06F15/00 , G06F11/00
CPC分类号： G06F9/30185 , G06F9/30189 , G06F9/3851 , G06F9/4843
摘要： A method and a device for controlling a computer system having at least two execution units, switchover operations being carried out between at least two operating modes, and a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode. At least one set of runtime objects is defined; at least one identifier is assigned to each runtime object of the defined set; and the identifier assigns at least the two operating modes to the runtime object.
摘要翻译：一种用于控制具有至少两个执行单元的计算机系统的方法和装置，在至少两个操作模式之间执行切换操作，以及对应于比较模式的第一操作模式和对应于演奏模式的第二操作模式。至少定义一组运行时对象; 至少一个标识符被分配给定义的集合的每个运行时对象; 并且标识符至少将两种操作模式分配给运行时对象。

89. 发明授权

US08190971B2 Data processing system and method for operating a data processing system 有权
标题翻译：用于操作数据处理系统的数据处理系统和方法
公开(公告)号：US08190971B2
公开(公告)日：2012-05-29
申请号：US12065454
申请日：2006-07-28
申请人： Reinhard Weiberle , Eberhard Boehl
发明人： Reinhard Weiberle , Eberhard Boehl
IPC分类号： G11C29/00
CPC分类号： G06F11/1008 , G11C29/42 , G11C29/52 , G11C2029/0401 , G11C2029/0409 , G11C2029/0411
摘要： To improve the availability of a data processing system despite possible memory errors, when reading a data word from a memory cell, the integrity of the data word is checked on the basis of redundant additional information, and if the data word turns out to be corrupted, an error correction procedure is performed in which the reliability performance of the memory cell is checked and, if the memory cell is found to be operational, its contents are restored.
摘要翻译：为了提高数据处理系统的可用性，尽管存在可能的存储器错误，当从存储器单元读取数据字时，基于冗余附加信息检查数据字的完整性，并且如果数据字被证明已被破坏执行检查存储单元的可靠性的错误校正过程，并且如果存储单元被发现可操作，则其内容被恢复。

90. 发明授权

US08090983B2 Method and device for performing switchover operations in a computer system having at least two execution units 有权
标题翻译：在具有至少两个执行单元的计算机系统中执行切换操作的方法和装置
公开(公告)号：US08090983B2
公开(公告)日：2012-01-03
申请号：US11666184
申请日：2005-10-25
申请人： Reinhard Weiberle , Bernd Mueller , Eberhard Boehl , Yorck Von Collani , Rainer Gmehlich
发明人： Reinhard Weiberle , Bernd Mueller , Eberhard Boehl , Yorck Von Collani , Rainer Gmehlich
IPC分类号： G06F15/80
CPC分类号： G06F9/3851 , G06F9/30076 , G06F9/30189 , G06F9/3885 , G06F11/1641 , G06F11/1695 , G06F2201/845
摘要： A method and device for performing switchover operations in a computer system having at least two execution units are provided, in which switchover units are included which are configured in such a way that they switch over between at least two operating modes, a first operating mode corresponding to a compare mode, and a second operating mode corresponding to a performance mode. An interrupt controller is provided and, furthermore, at least three memory areas are provided, and the access to the memory areas is implemented in such a way that one first memory area is assigned to at least one first execution unit, and one second memory area is assigned to the at least one second execution unit, and at least one third memory area is assignable to the at least two execution units.
摘要翻译：提供一种用于在具有至少两个执行单元的计算机系统中进行切换操作的方法和装置，其中包括切换单元，其以这样的方式配置，使得它们在至少两个操作模式之间切换，第一操作模式对应到比较模式和对应于演奏模式的第二操作模式。提供了中断控制器，此外，提供了至少三个存储区域，并且以这样的方式实现对存储区域的访问，使得一个第一存储区域被分配给至少一个第一执行单元和一个第二存储区域被分配给所述至少一个第二执行单元，并且至少一个第三存储器区域可分配给所述至少两个执行单元。

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