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81. 发明申请

US20110089311A1 TRENCH TRANSFER GATE FOR INCREASED PIXEL FILL FACTOR 有权
标题翻译：用于增加像素填充因子的TRENCH转移门
公开(公告)号：US20110089311A1
公开(公告)日：2011-04-21
申请号：US12582585
申请日：2009-10-20
申请人： Vincent Venezia , Hsin-Chih Tai , Duli Mao , Howard E. Rhodes
发明人： Vincent Venezia , Hsin-Chih Tai , Duli Mao , Howard E. Rhodes
IPC分类号： H01L31/112 , H01L27/00
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14643 , H01L27/14689
摘要： An image sensor provides high scalability and reduced image lag. The sensor includes a first imaging pixel that has a first photodiode region formed in a substrate of the image sensor. The sensor also includes a first vertical transfer transistor coupled to the first photodiode region. The first vertical transfer transistor can be used to establish an active channel. The active channel typically extends along the length of the first vertical transfer transistor and couples the first photodiode region to a floating diffusion.
摘要翻译：图像传感器提供高可扩展性和减少图像滞后。传感器包括具有形成在图像传感器的基板中的第一光电二极管区域的第一成像像素。传感器还包括耦合到第一光电二极管区域的第一垂直传输晶体管。第一垂直传输晶体管可用于建立有源通道。有源沟道通常沿着第一垂直传输晶体管的长度延伸，并将第一光电二极管区域耦合到浮动扩散。

82. 发明申请

US20100038523A1 IMAGE SENSOR WITH BURIED SELF ALIGNED FOCUSING ELEMENT 有权
标题翻译：具有自由自对准聚焦元件的图像传感器
公开(公告)号：US20100038523A1
公开(公告)日：2010-02-18
申请号：US12559307
申请日：2009-09-14
申请人： Vincent Venezia , Hsin-Chih Tai , Duli Mao , Ashish Shah , Howard E. Rhodes
发明人： Vincent Venezia , Hsin-Chih Tai , Duli Mao , Ashish Shah , Howard E. Rhodes
IPC分类号： H01J40/14 , H01L31/18
CPC分类号： H01L27/14685 , H01L27/14621 , H01L27/14627 , H01L27/14629 , H01L27/14636 , H01L27/14643
摘要： An image sensor includes an optical sensor region, a stack of dielectric and metal layers, and an embedded layer. The optical sensor is disposed within a semiconductor substrate. The stack of dielectric and metal layers are disposed on the front side of the semiconductor substrate above the optical sensor region. The embedded focusing layer is disposed on the backside of the semiconductor substrate in a Backside Illuminated (BSI) image sensor, supported by a support grid, or a support grid composed of the semiconductor substrate.
摘要翻译：图像传感器包括光学传感器区域，电介质和金属层的堆叠以及嵌入层。光学传感器设置在半导体衬底内。电介质层和金属层堆叠在光学传感器区域上方的半导体衬底的前侧。嵌入式聚焦层设置在由支撑栅格支撑的背面照明（BSI）图像传感器或由半导体衬底组成的支撑栅格上的半导体衬底的背面。

83. 发明申请

US20090200586A1 BACKSIDE ILLUMINATED IMAGING SENSOR WITH SILICIDE LIGHT REFLECTING LAYER 有权
标题翻译：背面照明成像传感器与硅光反射层
公开(公告)号：US20090200586A1
公开(公告)日：2009-08-13
申请号：US12142678
申请日：2008-06-19
申请人： Duli Mao , Hsin-Chih Tai , Vincent Venezia , Howard E. Rhodes
发明人： Duli Mao , Hsin-Chih Tai , Vincent Venezia , Howard E. Rhodes
IPC分类号： H01L27/146
CPC分类号： H01L27/14625 , H01L27/1464 , H01L27/14643
摘要： A backside illuminated imaging sensor includes a semiconductor layer, a metal interconnect layer and a silicide light reflecting layer. The semiconductor layer has a front surface and a back surface. An imaging pixel that includes a photodiode region is formed within the semiconductor layer. The metal interconnect layer is electrically coupled to the photodiode region and the silicide light reflecting layer is coupled between the metal interconnect layer and the front surface of the semiconductor layer. In operation, the photodiode region receives light from the back surface of the semiconductor layer, where a portion of the received light propagates through the photodiode region to the silicide light reflecting layer. The silicide light reflecting layer is configured to reflect the portion of light received from the photodiode region.
摘要翻译：背面照明成像传感器包括半导体层，金属互连层和硅化物光反射层。半导体层具有前表面和后表面。在半导体层内形成包括光电二极管区域的成像像素。金属互连层电耦合到光电二极管区域，并且硅化物光反射层耦合在金属互连层和半导体层的前表面之间。在操作中，光电二极管区域从半导体层的背面接收光，其中接收的光的一部分通过光电二极管区域传播到硅化物光反射层。硅化物光反射层被配置为反射从光电二极管区域接收的光的部分。

84. 发明申请

US20140014813A1 INTEGRATED CIRCUIT STACK WITH INTEGRATED ELECTROMAGNETIC INTERFERENCE SHIELDING 有权
标题翻译：具有集成电磁干扰屏蔽的集成电路堆栈
公开(公告)号：US20140014813A1
公开(公告)日：2014-01-16
申请号：US13547997
申请日：2012-07-12
申请人： Duli Mao , Hsin-Chih Tai , Yin Qian , Tiejun Dai , Howard E. Rhodes , Hongli Yang
发明人： Duli Mao , Hsin-Chih Tai , Yin Qian , Tiejun Dai , Howard E. Rhodes , Hongli Yang
IPC分类号： H01L23/552 , H01L27/146
CPC分类号： H01L27/14623 , H01L27/14634 , H01L27/1464 , H01L27/1469
摘要： An integrated circuit system includes a first device wafer having a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer having a second semiconductor layer proximate to a second metal layer including a second conductor is disposed within a second metal layer oxide. A frontside of the first device wafer is bonded to a frontside of the second device wafer at a bonding interface. A conductive path couples the first conductor to the second conductor through the bonding interface. A first metal EMI shield is disposed in one of the first metal oxide layer and second metal layer oxide layer. The first EMI shield is included in a metal layer of said one of the first metal oxide layer and the second metal layer oxide layer nearest to the bonding interface.
摘要翻译：集成电路系统包括具有靠近第一金属层的第一半导体层的第一器件晶片，第一金属层包括设置在第一金属层氧化物内的第一导体。具有靠近包括第二导体的第二金属层的第二半导体层的第二器件晶片设置在第二金属层氧化物内。第一器件晶片的前端在接合界面处结合到第二器件晶片的前侧。导电路径通过接合界面将第一导体耦合到第二导体。第一金属EMI屏蔽设置在第一金属氧化物层和第二金属层氧化物层之一中。第一EMI屏蔽包括在最靠近接合界面的第一金属氧化物层和第二金属层氧化物层中的所述一个的金属层中。

85. 发明申请

US20130264688A1 METHOD AND APPARATUS PROVIDING INTEGRATED CIRCUIT SYSTEM WITH INTERCONNECTED STACKED DEVICE WAFERS 审中-公开
标题翻译：提供具有互连堆叠器件波形的集成电路系统的方法和装置
公开(公告)号：US20130264688A1
公开(公告)日：2013-10-10
申请号：US13441627
申请日：2012-04-06
申请人： Yin Qian , Hsin-Chih Tai , Duli Mao , Tiejun Dai , Howard E. Rhodes , Hongli Yang
发明人： Yin Qian , Hsin-Chih Tai , Duli Mao , Tiejun Dai , Howard E. Rhodes , Hongli Yang
IPC分类号： H01L29/06 , H01L21/28
CPC分类号： H01L24/80 , H01L21/76898 , H01L23/481 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L27/14634 , H01L2224/04042 , H01L2224/05567 , H01L2224/05571 , H01L2224/08145 , H01L2224/2401 , H01L2224/24105 , H01L2224/24147 , H01L2224/48151 , H01L2224/73251 , H01L2224/80357 , H01L2224/80896 , H01L2224/80986 , H01L2224/82031 , H01L2224/82106 , H01L2224/9202 , H01L2224/94 , H01L2225/06544 , H01L2924/00014 , H01L2924/14 , H01L2924/1433 , H01L2924/3511 , H01L2224/80001 , H01L2924/00012 , H01L2224/05552
摘要： An integrated circuit system includes a first device wafer that has a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer that has a second semiconductor layer proximate to a second metal layer including a second conductor disposed within a second metal layer oxide is also included. A frontside of the first metal layer oxide is bonded to a frontside of the second metal layer oxide at an oxide bonding interface between the first metal layer oxide and the second metal layer oxide. A conductive path couples the first conductor to the second conductor with conductive material formed in a cavity etched between the first conductor and the second conductor and etched through the oxide bonding interface and through the second semiconductor layer from a backside of the second device wafer.
摘要翻译：集成电路系统包括具有靠近第一金属层的第一半导体层的第一器件晶片，第一金属层包括设置在第一金属层氧化物内的第一导体。还包括具有靠近第二金属层的第二半导体层的第二器件晶片，该第二金属层包括设置在第二金属层氧化物内的第二导体。在第一金属层氧化物和第二金属层氧化物之间的氧化物接合界面处，第一金属层氧化物的前侧结合到第二金属层氧化物的前侧。导电路径将第一导体耦合到第二导体，导电材料形成在蚀刻在第一导体和第二导体之间的空腔中，并通过氧化物接合界面从第二器件晶片的背面蚀刻穿过第二半导体层。

86. 发明授权

US08933544B2 Integrated circuit stack with integrated electromagnetic interference shielding 有权
标题翻译：具有集成电磁干扰屏蔽的集成电路堆栈
公开(公告)号：US08933544B2
公开(公告)日：2015-01-13
申请号：US13547997
申请日：2012-07-12
申请人： Duli Mao , Hsin-Chih Tai , Yin Qian , Tiejun Dai , Howard E. Rhodes , Hongli Yang
发明人： Duli Mao , Hsin-Chih Tai , Yin Qian , Tiejun Dai , Howard E. Rhodes , Hongli Yang
IPC分类号： H01L23/552 , H01L27/146
CPC分类号： H01L27/14623 , H01L27/14634 , H01L27/1464 , H01L27/1469
摘要： An integrated circuit system includes a first device wafer having a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer having a second semiconductor layer proximate to a second metal layer including a second conductor is disposed within a second metal layer oxide. A frontside of the first device wafer is bonded to a frontside of the second device wafer at a bonding interface. A conductive path couples the first conductor to the second conductor through the bonding interface. A first metal EMI shield is disposed in one of the first metal oxide layer and second metal layer oxide layer. The first EMI shield is included in a metal layer of said one of the first metal oxide layer and the second metal layer oxide layer nearest to the bonding interface.
摘要翻译：集成电路系统包括具有靠近第一金属层的第一半导体层的第一器件晶片，第一金属层包括设置在第一金属层氧化物内的第一导体。具有靠近包括第二导体的第二金属层的第二半导体层的第二器件晶片设置在第二金属层氧化物内。第一器件晶片的前端在接合界面处结合到第二器件晶片的前侧。导电路径通过接合界面将第一导体耦合到第二导体。第一金属EMI屏蔽设置在第一金属氧化物层和第二金属层氧化物层之一中。第一EMI屏蔽包括在最靠近接合界面的第一金属氧化物层和第二金属层氧化物层中的所述一个的金属层中。

87. 发明授权

US09236411B2 Color filter patterning using hard mask 有权
标题翻译：使用硬掩模进行彩色滤光片图案化
公开(公告)号：US09236411B2
公开(公告)日：2016-01-12
申请号：US13197568
申请日：2011-08-03
申请人： Gang Chen , Duli Mao , Hsin-Chih Tai , Howard E. Rhodes
发明人： Gang Chen , Duli Mao , Hsin-Chih Tai , Howard E. Rhodes
IPC分类号： H01L29/49 , H01L27/146
CPC分类号： H01L27/14621 , H01L27/1464 , H01L27/14685
摘要： Embodiments are disclosed of an apparatus comprising a color filter arrangement including a set of color filters. The set of color filters includes a pair of first color filters, each having first and second hard mask layers formed thereon, a second color filter having the first hard mask layer formed thereon, and a third color filter having no hard mask layer formed thereon. Other embodiments are disclosed and claimed.
摘要翻译：公开了一种包括包括一组滤色器的滤色器装置的装置的实施例。该组滤色器包括一对第一和第二硬掩模层形成在其上的第一滤色器，其上形成有第一硬掩模层的第二滤色器和不形成硬掩模层的第三滤色器。公开和要求保护其他实施例。

88. 发明授权

US08952309B2 Image sensor with micro-lens coating 有权
标题翻译：具有微透镜涂层的图像传感器
公开(公告)号：US08952309B2
公开(公告)日：2015-02-10
申请号：US13252883
申请日：2011-10-04
申请人： Gang Chen , Hsin-Chih Tai , Duli Mao , Howard E. Rhodes
发明人： Gang Chen , Hsin-Chih Tai , Duli Mao , Howard E. Rhodes
IPC分类号： H01L27/148 , H01L27/146
CPC分类号： H01L27/14627 , H01L27/14685 , Y10T29/49885
摘要： Techniques and architectures for providing a coating for one or more micro-lenses of a pixel array. In an embodiment, a pixel element includes a micro-lens and a coating portion extending over a surface of the micro-lens, where a profile of the coating portion is super-conformal to, or at least conformal to, a profile of the micro-lens. In another embodiment, the coating portion is formed at least in part by orienting the surface of the micro-lens to face generally downward with the direction of gravity, the orienting to allow a fluid coating material to flow for formation of the coating portion.
摘要翻译：用于为像素阵列的一个或多个微透镜提供涂层的技术和架构。在一个实施例中，像素元件包括微透镜和在微透镜的表面上延伸的涂层部分，其中涂层部分的轮廓与微观透镜的轮廓超共形或至少共形 -镜片。在另一个实施例中，涂覆部分至少部分地通过使微透镜的表面定向以与重力方向大致向下的方式形成，定向以允许流体涂覆材料流动以形成涂覆部分。

89. 发明授权

US08497536B2 Dual-facing camera assembly 有权
标题翻译：双面相机组合
公开(公告)号：US08497536B2
公开(公告)日：2013-07-30
申请号：US13235121
申请日：2011-09-16
申请人： Gang Chen , Ashish Shah , Duli Mao , Hsin-Chih Tai , Howard E. Rhodes
发明人： Gang Chen , Ashish Shah , Duli Mao , Hsin-Chih Tai , Howard E. Rhodes
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H01L27/14645 , H01L27/14605 , H01L27/1462 , H01L27/14621 , H01L27/14627 , H01L27/14634 , H01L27/14636 , H01L27/1464 , H01L27/1469
摘要： Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate).In some embodiments of the invention, a system having an array of frontside illuminated (FSI) imaging pixels is bonded to a system having an array of backside illuminated (BSI) imaging pixels, creating a camera assembly with a minimal size (e.g., a reduced thickness compared to prior art solutions). An FSI image sensor wafer may be used as a handle wafer for a BSI image sensor wafer when it is thinned, thereby decreasing the thickness of the overall camera module. According to other embodiments of the invention, two package dies, one a BSI image sensor, the other an FSI image sensor, are stacked on a common substrate such as a printed circuit board, and are operatively coupled together via redistribution layers.
摘要翻译：本发明的实施例涉及一种照相机组件，其包括背面照相机和可操作地耦合在一起的例如相机（例如，粘合的，堆叠在公共衬底上）的前置照相机。在本发明的一些实施例中，具有前侧照明（FSI）成像像素阵列的系统被结合到具有背面照明（BSI）成像像素阵列的系统，从而产生具有最小尺寸的照相机组件（例如，减小的厚度与现有技术的解决方案相比）。可以使用FSI图像传感器晶片作为BSI图像传感器晶片的处理晶片，当其变薄时，从而减小整个相机模块的厚度。根据本发明的其它实施例，两个封装管芯，一个BSI图像传感器，另一个是FSI图像传感器，堆叠在诸如印刷电路板的公共基板上，并且通过再分配层可操作地耦合在一起。

90. 发明申请

US20130033627A1 COLOR FILTER PATTERNING USING HARD MASK 有权
标题翻译：使用硬面罩的彩色滤镜图案
公开(公告)号：US20130033627A1
公开(公告)日：2013-02-07
申请号：US13197568
申请日：2011-08-03
申请人： Gang Chen , Duli Mao , Hsin-Chih Tai , Howard E. Rhodes
发明人： Gang Chen , Duli Mao , Hsin-Chih Tai , Howard E. Rhodes
IPC分类号： H04N9/07 , G02B5/22 , B44C1/22
CPC分类号： H01L27/14621 , H01L27/1464 , H01L27/14685
摘要： Embodiments are disclosed of an apparatus comprising a color filter arrangement including a set of color filters. The set of color filters includes a pair of first color filters, each having first and second hard mask layers formed thereon, a second color filter having the first hard mask layer formed thereon, and a third color filter having no hard mask layer formed thereon. Other embodiments are disclosed and claimed.
摘要翻译：公开了一种包括包括一组滤色器的滤色器装置的装置的实施例。该组滤色器包括一对第一和第二硬掩模层形成在其上的第一滤色器，其上形成有第一硬掩模层的第二滤色器和不形成硬掩模层的第三滤色器。公开和要求保护其他实施例。

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