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81. 发明授权

US06721222B2 Noise suppression for open bit line DRAM architectures 有权
标题翻译：开放位线DRAM架构的噪声抑制
公开(公告)号：US06721222B2
公开(公告)日：2004-04-13
申请号：US10300398
申请日：2002-11-19
申请人： Dinesh Somasekhar , Shih-Lien L. Lu , Vivek K. De
发明人： Dinesh Somasekhar , Shih-Lien L. Lu , Vivek K. De
IPC分类号： G11C702
CPC分类号： G11C11/4097 , G11C7/02 , G11C11/4094
摘要： An open bit line dynamic random access memory (DRAM) architecture uses a multiple layer bit line configuration to reduce coupling between switching bit lines in the device. In one approach, each successive cell within a row of DRAM cells is coupled to a bit line segment that is on a different metallization layer than a previous cell in the row. Shielding members are also provided between adjacent bit lines on a common metallization layer to further reduce noise coupling. Functionality is also provided for reducing the effect of word line to bit line coupling in the DRAM device using dummy signal injection techniques. In this manner, common mode noise that could otherwise saturate one or more sense amplifiers within the DRAM device is reduced or eliminated before such saturation can take place. In one approach, dummy cells and reference cells are provided for use in performing the signal injection. The principles of the present invention are particularly well suited for use within embedded DRAM structures where low charge storage capacity within individual cells reduces the signal voltage levels that are achievable.
摘要翻译：开放式位线动态随机存取存储器（DRAM）架构使用多层位线配置来减少器件中的开关位线之间的耦合。在一种方法中，DRAM单元行内的每个连续单元被耦合到位于与行中的先前单元格不同的金属化层上的位线段。屏蔽构件也设置在公共金属化层上的相邻位线之间，以进一步减少噪声耦合。还提供了功能，用于使用虚拟信号注入技术来减少DRAM设备中字线对位线耦合的影响。以这种方式，在这种饱和可能发生之前，可以减少或消除在DRAM装置内可以饱和一个或多个感测放大器的共模噪声。在一种方法中，提供虚拟单元和参考单元用于执行信号注入。本发明的原理特别适用于嵌入式DRAM结构，其中各个单元内的低电荷存储容量降低了可实现的信号电压电平。

82. 发明授权

US06567329B2 Multiple word-line accessing and accessor 有权
标题翻译：多个字线访问和访问器
公开(公告)号：US06567329B2
公开(公告)日：2003-05-20
申请号：US09941053
申请日：2001-08-28
申请人： Dinesh Somasekhar , Shih-Lien L. Lu , Vivek K. De
发明人： Dinesh Somasekhar , Shih-Lien L. Lu , Vivek K. De
IPC分类号： G11C702
CPC分类号： G11C11/408 , G11C11/4097
摘要： The word-lines and/or bit-lines in a memory are physically arranged to reduce capacitive coupling between signal lines and reference lines. In one embodiment the two bit lines connected to a single sense amplifier are physically separated from each other by bit lines connected to other sense amplifiers. In another embodiment the word-lines are separated from each other by placing them in different metallization layers. In a particular embodiment a single word-line has different portions disposed in different metallization layers.
摘要翻译：物理地布置存储器中的字线和/或位线以减少信号线和参考线之间的电容耦合。在一个实施例中，连接到单个读出放大器的两个位线通过连接到其它读出放大器的位线彼此物理分离。在另一个实施例中，字线通过将它们放置在不同的金属化层中而彼此分离。在特定实施例中，单个字线具有设置在不同金属化层中的不同部分。

83. 发明申请

US20130003469A1 CIRCUITS AND METHODS FOR MEMORY 有权
标题翻译：存储器的电路和方法
公开(公告)号：US20130003469A1
公开(公告)日：2013-01-03
申请号：US13174352
申请日：2011-06-30
申请人： Jaydeep P. Kulkarni , Dinesh Somasekhar , James W. Tschanz , Vivek K. De
发明人： Jaydeep P. Kulkarni , Dinesh Somasekhar , James W. Tschanz , Vivek K. De
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C11/419
摘要： Embodiments for data dependent boosted (DDB) bit cells that may allow for smaller minimum cell supplies (Vmin) without necessarily having to increase device dimensions are presented.
摘要翻译：呈现可能允许更小的最小电池电源（Vmin）的数据相关升压（DDB）位单元的实施例，而不必增加器件尺寸。

84. 发明申请

US20070058419A1 Memory cell having p-type pass device 有权
公开(公告)号：US20070058419A1
公开(公告)日：2007-03-15
申请号：US11225912
申请日：2005-09-13
申请人： Muhammad Khellah , Dinesh Somasekhar , Nam Kim , Yibin Ye , Vivek De , Kevin Zhang , Bo Zheng
发明人： Muhammad Khellah , Dinesh Somasekhar , Nam Kim , Yibin Ye , Vivek De , Kevin Zhang , Bo Zheng
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , Y10S257/903
摘要： For one disclosed embodiment, an apparatus comprises a first p-type device coupled between a cell voltage node and a storage node, an n-type device coupled between the storage node and a reference voltage node, and a second p-type device to couple the storage node to a bit line in response to a signal on a select line. At least one side of diffusion regions in a substrate to form both the first p-type device and the second p-type device are substantially aligned. Other embodiments are also disclosed.

85. 发明申请

US20070002607A1 Memory circuit 审中-公开
标题翻译：存储电路
公开(公告)号：US20070002607A1
公开(公告)日：2007-01-04
申请号：US11172078
申请日：2005-06-29
申请人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De
发明人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De
IPC分类号： G11C11/00
CPC分类号： G11C11/419
摘要： In some embodiments, a memory array is provided comprising columns of SRAM bit cells, the columns each comprising a bit line and a sense amplifier coupled to the bit line, the sense amplifier to maintain a state in a selected cell of its bit line during a read operation. Other embodiments are disclosed herein.
摘要翻译：在一些实施例中，提供了包括SRAM位单元列的存储器阵列，每个列包括位线和耦合到位线的读出放大器，读出放大器在一段时间内维持其位线的选定单元格中的状态读操作。本文公开了其它实施例。

86. 发明申请

US20060267093A1 Floating-body dynamic random access memory and method of fabrication in tri-gate technology 有权
公开(公告)号：US20060267093A1
公开(公告)日：2006-11-30
申请号：US11429490
申请日：2006-05-04
申请人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Brian Doyle , Suman Datta , Vivek De
发明人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Brian Doyle , Suman Datta , Vivek De
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/66795 , H01L29/7841
摘要： A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

87. 发明申请

US20060187706A1 2-Transistor floating-body dram 有权
标题翻译： 2晶体管浮体电容
公开(公告)号：US20060187706A1
公开(公告)日：2006-08-24
申请号：US11008666
申请日：2005-02-22
申请人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
发明人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
IPC分类号： G11C11/34
CPC分类号： G11C11/405 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.
摘要翻译：动态随机存取存储器包括具有浮体晶体管和位线之间的电路的单元。控制电路的激活以在写入操作期间和在单元未被选择的时间期间在浮体和位线电压之间提供隔离。增加的隔离可以提高性能，例如，通过减少门到体耦合的需要和位线之间的电压摆幅的大小。

88. 发明申请

US20060139995A1 One time programmable memory 审中-公开
标题翻译：一次可编程存储器
公开(公告)号：US20060139995A1
公开(公告)日：2006-06-29
申请号：US11027476
申请日：2004-12-28
申请人： Ali Keshavarzi , Fabrice Paillet , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De
发明人： Ali Keshavarzi , Fabrice Paillet , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De
IPC分类号： G11C11/34
CPC分类号： G11C17/146 , G11C17/12
摘要： A one time programmable memory includes isolated gate transistors that may be programmed by subjecting the isolated gate transistors to voltage conditions that degrade characteristics of the isolated gate transistors. The degraded characteristics may be sensed to read the memory.
摘要翻译：一次性可编程存储器包括隔离栅极晶体管，其可以通过使隔离栅极晶体管受到降低隔离栅极晶体管特性的电压条件而被编程。可以感测劣化的特性以读取存储器。

89. 发明申请

US20060098482A1 Floating-body dynamic random access memory with purge line 失效
公开(公告)号：US20060098482A1
公开(公告)日：2006-05-11
申请号：US11289621
申请日：2005-11-30
申请人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
发明人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
IPC分类号： G11C11/34
CPC分类号： H01L27/108 , G11C11/404
摘要： Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.

90. 发明申请

US20050285616A1 Overvoltage detection apparatus, method, and system 有权
标题翻译：过电压检测装置，方法和系统
公开(公告)号：US20050285616A1
公开(公告)日：2005-12-29
申请号：US10880337
申请日：2004-06-29
申请人： Ali Keshavarzi , Fabrice Paillet , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De
发明人： Ali Keshavarzi , Fabrice Paillet , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De
IPC分类号： G01R19/165 , G01R31/26
CPC分类号： G01R31/2621 , G01R19/16571
摘要： A transistor may have degraded characteristics because of an overvoltage condition. The degraded characteristics may be sensed to determine that the transistor has previously been subjected to an overvoltage condition.
摘要翻译：由于过电压状态，晶体管可能具有劣化特性。可以感测劣化特性以确定晶体管先前已经经受过压状态。

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