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81. 发明授权

US07620126B2 Method and apparatus for detecting frequency lock in a system including a frequency synthesizer 失效
标题翻译：用于检测包括频率合成器的系统中的频率锁定的方法和装置
公开(公告)号：US07620126B2
公开(公告)日：2009-11-17
申请号：US11236658
申请日：2005-09-27
申请人： David William Boerstler , Matthew E. Fernsler , Eskinder Hailu , Jieming Qi , Mack Wayne Riley
发明人： David William Boerstler , Matthew E. Fernsler , Eskinder Hailu , Jieming Qi , Mack Wayne Riley
IPC分类号： H03D3/18
CPC分类号： H03L7/093 , H03L7/095
摘要： A frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.
摘要翻译：公开了一种频率合成器锁定检测系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。

82. 发明申请

US20090112555A1 Design Structure For A Duty Cycle Measurement Apparatus That Operates In A Calibration Mode And A Test Mode 失效
标题翻译：在校准模式和测试模式下工作的占空比测量装置的设计结构
公开(公告)号：US20090112555A1
公开(公告)日：2009-04-30
申请号：US12347853
申请日：2008-12-31
申请人： David William Boerstler , Eskinder Hailu , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F17/50
CPC分类号： G01R31/31727
摘要： A design structure for an on-chip duty cycle measurement system may be embodied in a machine readable medium for designing, manufacturing or testing an integrated circuit. The design structure may embody an apparatus that measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. The design structure may specify that the DCM circuit includes a capacitor driven by a charge pump and that a reference clock signal drives the charge pump. The design structure may specify that the clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The design structure may specify that the DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit may apply a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. The design structure may specify that control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.
摘要翻译：用于片上占空比测量系统的设计结构可以体现在用于设计，制造或测试集成电路的机器可读介质中。该设计结构可以体现测量时钟电路提供给占空比测量（DCM）电路的参考时钟信号的占空比的装置。设计结构可以指定DCM电路包括由电荷泵驱动的电容器，并且参考时钟信号驱动电荷泵。设计结构可以指定时钟电路在多个已知占空比值之间改变参考时钟信号的占空比。该设计结构可以指定DCM电路将对应于每个已知占空比值的合成电容电压值存储在数据存储器中。 DCM电路可以通过电荷泵向电容器施加具有未知占空比的测试时钟信号，从而将电容器充电到对应于测试时钟信号占空比的新电压值。设计结构可以指定控制软件访问数据存储以确定测试时钟信号对应的占空比。

83. 发明申请

US20080174345A1 METHOD AND APPARATUS FOR MEASURING THE DUTY CYCLE OF A DIGITAL SIGNAL 有权
标题翻译：用于测量数字信号占空比的方法和装置
公开(公告)号：US20080174345A1
公开(公告)日：2008-07-24
申请号：US11931879
申请日：2007-10-31
申请人： David William Boerstler , Eskinder Hailu , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K21/16
CPC分类号： G01R29/02 , G01R31/31725 , G01R31/31726
摘要： The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value that it receives. The variable duty cycle circuit supplies a duty-cycle adjusted clock signal to a divider circuit. The apparatus sweeps the frequency of the clock signal from a starting value up to a maximum frequency above which the divider circuit fails. The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal from the maximum frequency.
摘要翻译：所公开的方法和装置测量时钟信号的占空比。可变占空比电路从时钟信号发生器接收时钟信号。可变占空比电路根据其接收到的占空比指数值来调整时钟信号的占空比。可变占空比电路将占空比调整的时钟信号提供给分频器电路。该装置将时钟信号的频率从起始值扫描到高于分频器电路故障的最大频率。然后，该装置从最大频率确定占空比调整的时钟信号的占空比。

84. 发明授权

US07350095B2 Digital circuit to measure and/or correct duty cycles 有权
标题翻译：用于测量和/或校正占空比的数字电路
公开(公告)号：US07350095B2
公开(公告)日：2008-03-25
申请号：US11082973
申请日：2005-03-17
申请人： David William Boerstler , Eskinder Hailu , Byron Lee Krauter , Kazuhiko Miki , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Byron Lee Krauter , Kazuhiko Miki , Jieming Qi
IPC分类号： G06F1/00 , G06F1/12 , G06F1/04
CPC分类号： G06F1/10 , H03K5/1565
摘要： A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.
摘要翻译：提供了一种方法，装置和计算机程序来测量和/或校正占空比。各种信号的占空比，特别是时钟信号是很重要的。然而，测量非常高频率的信号，芯片外和实验室环境可能是非常困难的并且存在许多问题。为了解决与片外测量和信号占空比调整相关的问题，可以比较输入信号和分频输入信号，从而便于测量和调整片上信号，包括时钟信号。

85. 发明申请

US20070300113A1 Apparatus and Method for Automatically Self-Calibrating a Duty Cycle Circuit for Maximum Chip Performance 有权
标题翻译：用于自动校准占空比电路以实现最大芯片性能的装置和方法
公开(公告)号：US20070300113A1
公开(公告)日：2007-12-27
申请号：US11848314
申请日：2007-08-31
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F11/27
CPC分类号： H03K5/1565 , G01R31/31727 , G01R31/3187
摘要： An apparatus and method for automatically calibrating a duty cycle circuit for maximum performance are provided. A chip level built-in circuit that automatically calibrates the duty cycle correction (DCC) circuit setting for each chip is provided. This chip level built-in circuit includes a clock generation macro unit, a simple duty cycle correction (DCC) circuit, an array slice and built-in self test unit, and a DCC circuit controller. Results of a built-in self test, i.e. pass or fail, of an array are provided to the DCC circuit controller. If the result of the built-in self test is a pass, then the current DCC circuit controller's DCC control bit setting is set as the setting for the chip. If the result from the built-in self test is a fail, the DCC circuit controller's DCC control bits setting is incremented to a next setting and the self-test is performed again.
摘要翻译：提供一种用于自动校准占空比电路以实现最大性能的装置和方法。提供了自动校准每个芯片的占空比校正（DCC）电路设置的芯片级内置电路。该芯片级内置电路包括时钟生成宏单元，简单占空比校正（DCC）电路，阵列片和内置自检单元以及DCC电路控制器。向DCC电路控制器提供阵列的内置自检，即通过或失败的结果。如果内置自检的结果是通过，则将当前DCC电路控制器的DCC控制位设置设置为芯片的设置。如果内置自检的结果为失败，DCC电路控制器的DCC控制位设置将增加到下一个设置，并再次执行自检。

86. 发明申请

US20070266285A1 DUTY CYCLE MEASUREMENT METHOD AND APPARATUS THAT OPERATES IN A CALIBRATION MODE AND A TEST MODE 有权
标题翻译：在校准模式和测试模式下运行的占空比测量方法和设备
公开(公告)号：US20070266285A1
公开(公告)日：2007-11-15
申请号：US11381031
申请日：2006-05-01
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G01R31/28
CPC分类号： G01R31/31727
摘要： The disclosed methodology and apparatus measure the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.
摘要翻译：所公开的方法和装置测量时钟电路提供给占空比测量（DCM）电路的参考时钟信号的占空比。在一个实施例中，DCM电路包括由电荷泵驱动的电容器。参考时钟信号驱动电荷泵。时钟电路在多个已知的占空比值之间改变参考时钟信号的占空比。 DCM电路将对应于每个已知占空比值的合成电容电压值存储在数据存储器中。 DCM电路通过电荷泵向电容器施加具有未知占空比的测试时钟信号，从而将电容器充电到对应于测试时钟信号占空比的新电压值。控制软件访问数据存储，以确定测试时钟信号对应的占空比。

87. 发明申请

US20070100505A1 Duty cycle measurement apparatus and method 失效
标题翻译：占空比测量装置及方法
公开(公告)号：US20070100505A1
公开(公告)日：2007-05-03
申请号：US11260570
申请日：2005-10-27
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G05D11/00
CPC分类号： G01R29/02 , G01R31/2884
摘要： A mechanism for measuring duty cycle of a signal under test in an integrated circuit device, such as a microprocessor or system-on-a-chip is provided. The mechanism generates a frequency which is proportional to the duty cycle and which can be measured using common lab or manufacturing equipment. The mechanism may be implemented using simple circuits in a standard complementary metal oxide semiconductor process which requires very little area and can be powered off when it is not being used. The mechanism may include, for example, a low pass filter, a voltage divider for providing calibration reference voltage signals, a voltage to frequency converter, a frequency divider for dividing a frequency signal output so that the frequency of the signal is within a predetermined range, and an output driver and output pad. From the frequency output signal, a duty cycle of the signal under test may be calculated using off-chip equipment.
摘要翻译：提供了一种用于测量诸如微处理器或片上系统的集成电路器件中被测信号占空比的机构。该机制产生与占空比成比例的频率，可以使用普通实验室或制造设备测量。该机构可以使用标准互补金属氧化物半导体工艺中的简单电路来实现，其需要非常小的面积并且可以在不使用时关闭电源。该机构可以包括例如低通滤波器，用于提供校准参考电压信号的分压器，电压到频率转换器，用于分频频率信号输出的分频器，使得信号的频率在预定范围内，以及输出驱动器和输出板。从频率输出信号，可以使用片外设备来计算被测信号的占空比。

88. 发明申请

US20070075764A1 Level shifter system and method to minimize duty cycle error due to voltage differences across power domains 失效
标题翻译：电平移位器系统和方法，可以最大限度地减少跨越电源域的电压差造成的占空比误差
公开(公告)号：US20070075764A1
公开(公告)日：2007-04-05
申请号：US11242670
申请日：2005-10-04
申请人： David Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
IPC分类号： H03L5/00
CPC分类号： H03K19/00384 , H03K5/1565 , H03K19/00323 , H03K19/00369 , H03K19/0175
摘要： The present invention provides for a system comprising a first stable voltage module configured to receive a first power supply from a first power supply domain and to generate a first stable voltage in response to the received first power supply. A second stable voltage module is configured to receive a second power supply from a second power supply domain and to generate a second stable voltage in response to the received second power supply. A first set of resistors is coupled to the first stable voltage module and configured in parallel. A second set of resistors is coupled to the second stable voltage module and configured in parallel. A set of capacitors is coupled in parallel to the first set of resistors and the second set of resistors and a plurality of level shifters are coupled to the second set of resistors.
摘要翻译：本发明提供了一种系统，其包括第一稳定电压模块，其被配置为从第一电源域接收第一电源并且响应于所接收的第一电源产生第一稳定电压。第二稳定电压模块被配置为从第二电源域接收第二电源并且响应于所接收的第二电源产生第二稳定电压。第一组电阻器耦合到第一稳定电压模块并且并联配置。第二组电阻器耦合到第二稳定电压模块并且并联配置。一组电容器并联耦合到第一组电阻器，并且第二组电阻器和多个电平移位器耦合到第二组电阻器。

89. 发明授权

US07132896B2 Circuit for minimizing filter capacitance leakage induced jitter in phase locked loops (PPLs) 有权
标题翻译：用于最小化锁相环（PPL）中的滤波电容泄漏引起的抖动的电路
公开(公告)号：US07132896B2
公开(公告)日：2006-11-07
申请号：US10981155
申请日：2004-11-04
申请人： David William Boerstler , Eskinder Hailu , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03L7/093 , H03L7/095 , H03B1/04
CPC分类号： H03L7/0893 , H03L7/093 , H03L7/095
摘要： A method, an apparatus, and a computer program are provided to minimize filter capacitor leakage in a Phased Locked Loop (PLL). In high frequency processors and devices, filter leakage currents can cause substantial problems by causing PLLs to drift out of phase lock. To combat the leakage currents, a dummy filter and other components are employed to provide additional charge or voltage to a low pass filter during lock. The provision of the charge or voltage exponentially decreases the rate of decay of voltage across the low pass filter caused by leakage currents.
摘要翻译：提供了一种方法，装置和计算机程序以最小化相位锁定环（PLL）中的滤波电容器泄漏。在高频处理器和器件中，滤波器漏电流可能会导致相位锁相位漂移出现相当大的问题。为了防止泄漏电流，使用虚拟滤波器和其他组件在锁定期间向低通滤波器提供额外的充电或电压。充电或电压的提供以指数方式降低由漏电流引起的低通滤波器的电压衰减速率。

90. 发明授权

US07917795B2 Digital circuit to measure and/or correct duty cycles 有权
标题翻译：用于测量和/或校正占空比的数字电路
公开(公告)号：US07917795B2
公开(公告)日：2011-03-29
申请号：US12014501
申请日：2008-01-15
申请人： David William Boerstler , Eskinder Hailu , Byron Lee Krauter , Kazuhiko Miki , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Byron Lee Krauter , Kazuhiko Miki , Jieming Qi
IPC分类号： G06F1/00 , G06F1/04 , H03K19/096 , H03K5/22 , H03K7/08 , H03K9/08 , H03L7/06 , G01R23/00 , G01M19/00
CPC分类号： G06F1/10 , H03K5/1565
摘要： A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.
摘要翻译：提供了一种方法，装置和计算机程序来测量和/或校正占空比。各种信号的占空比，特别是时钟信号是很重要的。然而，测量非常高频率的信号，芯片外和实验室环境可能是非常困难的并且存在许多问题。为了解决与片外测量和信号占空比调整相关的问题，可以比较输入信号和分频输入信号，从而便于测量和调整片上信号，包括时钟信号。

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