专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US06972250B2 Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe device 失效
标题翻译：通过垂直自对准CoSi2在升高的源极漏极Si / SiGe器件上形成的超低接触电阻CMOS的方法和结构
公开(公告)号：US06972250B2
公开(公告)日：2005-12-06
申请号：US10419888
申请日：2003-04-22
申请人： Cyril Cabral, Jr. , Roy A. Carruthers , Kevin K. Chan , Jack O. Chu , Guy Moshe Cohen , Steven J. Koester , Christian Lavoie , Ronnen A. Roy
发明人： Cyril Cabral, Jr. , Roy A. Carruthers , Kevin K. Chan , Jack O. Chu , Guy Moshe Cohen , Steven J. Koester , Christian Lavoie , Ronnen A. Roy
IPC分类号： H01L21/285 , H01L21/336 , H01L21/8238 , H01L29/161 , H01L21/4763
CPC分类号： H01L29/41783 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L29/161 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： A method (and structure) of forming a vertically-self-aligned silicide contact to an underlying SiGe layer, includes forming a layer of silicon of a first predetermined thickness on the SiGe layer and forming a layer of metal on the silicon layer, where the metal layer has a second predetermined thickness. A thermal annealing process at a predetermined temperature then forms a silicide of the silicon and metal, where the predetermined temperature is chosen to substantially preclude penetration of the silicide into the underlying SiGe layer.
摘要翻译：形成垂直自对准的硅化物接触到下面的SiGe层的方法（和结构）包括在SiGe层上形成第一预定厚度的硅层，并在硅层上形成一层金属，其中金属层具有第二预定厚度。然后在预定温度下的热退火工艺形成硅和金属的硅化物，其中选择预定温度以基本排除硅化物渗入下面的SiGe层。

82. 发明授权

US06831369B2 Semiconductor structure having in-situ formed unit resistors and method for fabrication 有权
标题翻译：具有原位形成单元电阻器的半导体结构和制造方法
公开(公告)号：US06831369B2
公开(公告)日：2004-12-14
申请号：US10705115
申请日：2003-11-10
申请人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
发明人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
IPC分类号： H01L2348
CPC分类号： H01L28/20 , H01L27/0688
摘要： An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.
摘要翻译：公开了一种具有原位形成的单位电阻器的电子结构及其制造方法。具有原位形成的单元电阻器的电子结构由形成在绝缘材料层中的第一多个导电元件组成，多个电阻通孔形成在顶部并与第一多个导电元件中的至少一个电连通以及形成在所述多个电阻通孔中的至少一个上方并与之电气连通的第二多个导电元件。本发明的新颖结构可以进一步形成为多电平配置，使得多电平电阻器可以串联连接以提供更大的电阻值。本发明的新颖结构还可以与电容器网络组合以形成期望的RC电路。

83. 发明授权

US06773982B2 Feram cell with internal oxygen source and method of oxygen release 失效
标题翻译：具有内氧源的Feram电池和释氧方法
公开(公告)号：US06773982B2
公开(公告)日：2004-08-10
申请号：US09927694
申请日：2001-08-10
申请人： Charles Thomas Black , Cyril Cabral, Jr. , Alfred Grill , Deborah Ann Neumayer , Wilbur David Pricer , Katherine Lynn Saenger , Thomas McCarroll Shaw
发明人： Charles Thomas Black , Cyril Cabral, Jr. , Alfred Grill , Deborah Ann Neumayer , Wilbur David Pricer , Katherine Lynn Saenger , Thomas McCarroll Shaw
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： An integrated ferroelectric/CMOS structure which comprises at least a ferroelectric material, a pair of electrodes in contact with opposite surfaces of the ferroelectric material, where the electrodes do not decompose at deposition or annealing, and an oxygen source layer in contact with at least one of said electrodes, said oxygen source layer being a metal oxide which at least partially decomposes during deposition and/or subsequent processing is provided as well as a method of fabricating the same.
摘要翻译：一种集成铁电/ CMOS结构，其至少包括铁电材料，与所述铁电材料的相对表面接触的一对电极，其中所述电极在沉积或退火时不分解，以及氧源层与至少一个的所述电极，所述氧源层是在沉积期间和/或后续处理中至少部分分解的金属氧化物以及其制造方法。

84. 发明授权

US06716708B2 Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby 有权
标题翻译：自对准硅化物工艺利用离子植入物降低硅消耗，并控制硅化物形成温度和由此形成的结构
公开(公告)号：US06716708B2
公开(公告)日：2004-04-06
申请号：US10299688
申请日：2002-11-20
申请人： Cyril Cabral, Jr. , Kevin Kok Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Ronnen Andrew Roy , Paul Michael Solomon
发明人： Cyril Cabral, Jr. , Kevin Kok Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Ronnen Andrew Roy , Paul Michael Solomon
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28052 , H01L21/28518 , H01L21/28525 , H01L29/41783
摘要： A method (and resultant structure) for forming a metal silicide contact on a silicon-containing region having controlled consumption of said silicon-containing region, includes implanting Ge into the silicon-containing region, forming a blanket metal-silicon mixture layer over the silicon-containing region, reacting the metal-silicon mixture with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal-silicon mixture layer, forming a blanket silicon layer over the metal silicon alloy layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.
摘要翻译：一种用于在具有所述含硅区域的受控消耗的含硅区域上形成金属硅化物接触的方法（和所得结构）包括将Ge注入含硅区域中，在硅上形成覆盖的金属 - 硅混合物层在第一温度下使金属硅混合物与硅反应以形成金属硅合金，蚀刻金属 - 硅混合物层的未反应部分，在金属硅合金层上形成覆盖硅层，在第二温度下退火温度以形成金属-Si2的合金，并且选择性地蚀刻未反应的硅层。

85. 发明授权

US06707097B2 Method for forming refractory metal-silicon-nitrogen capacitors and structures formed 有权
$Method for forming refractory metal-silicon-nitrogen capacitors and structures formed$
标题翻译：形成难熔金属 - 硅 - 氮电容器和结构的方法
公开(公告)号：US06707097B2
公开(公告)日：2004-03-16
申请号：US10346437
申请日：2003-01-16
申请人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Hsu , Keith Kwong Hon Wong
发明人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Hsu , Keith Kwong Hon Wong
IPC分类号： H01L218242
CPC分类号： H01L28/75 , C23C14/0073 , C23C14/0641 , H01L21/2855 , H01L21/28568
摘要： A method for forming a refractory metal-silicon-nitrogen capacitor in a semiconductor structure and the structure formed are described. In the method, a pre-processed semiconductor substrate is first positioned in a sputtering chamber. Ar gas is then flown into the sputtering chamber to sputter deposit a first refractory metal-silicon-nitrogen layer on the substrate from a refractory metal silicide target, or from two targets of a refractory metal and a silicon. N2 gas is then flown into the sputtering chamber until that the concentration of N2 gas in the chamber is at least 35% to sputter deposit a second refractory metal-silicon-nitrogen layer on top of the first refractory metal-silicon-nitrogen layer. The N2 gas flow is then stopped to sputter deposit a third refractory metal-silicon-nitrogen layer on top of the second refractory metal-silicon-nitrogen layer. The multi-layer stack of the refractory metal-silicon-nitrogen is then photolithographically formed into a capacitor.
摘要翻译：描述了在半导体结构中形成难熔金属 - 硅 - 氮电容器的方法和形成的结构。在该方法中，首先将预处理的半导体衬底定位在溅射室中。然后将Ar气体流入溅射室，以从耐火金属硅化物靶或从难熔金属和硅的两个靶溅射沉积在衬底上的第一难熔金属 - 硅 - 氮层。然后将N 2气体流入溅射室，直到室内的N 2气体的浓度至少为35％，以在第一难熔金属 - 硅 - 氮层的顶部溅射沉积第二难熔金属 - 硅 - 氮层。然后停止N 2气流以在第二难熔金属 - 硅 - 氮层的顶部溅射沉积第三难熔金属 - 硅 - 氮层。然后将难熔金属硅 - 氮的多层堆叠光刻形成电容器。

86. 发明授权

US06647614B1 Method for changing an electrical resistance of a resistor 失效
标题翻译：改变电阻器电阻的方法
公开(公告)号：US06647614B1
公开(公告)日：2003-11-18
申请号：US09693765
申请日：2000-10-20
申请人： Arne W. Ballantine , Cyril Cabral, Jr. , Daniel C. Edelstein , Anthony K. Stamper
发明人： Arne W. Ballantine , Cyril Cabral, Jr. , Daniel C. Edelstein , Anthony K. Stamper
IPC分类号： H01C1700
CPC分类号： H01L28/20 , H01C7/006 , H01C17/242 , Y10T29/49082 , Y10T29/49099 , Y10T29/49105
摘要： A method for changing an electrical resistance of a resistor. Initially, the resistor is provided, wherein the resistor has a length L and an electrical resistance R1. A portion of the resistor is exposed to a laser radiation, wherein the portion includes a fraction F of the length L of the resistor. After the resistor has been exposed to the laser radiation, the resistor has an electrical resistance R2, wherein R2 is unequal to R1.
摘要翻译：一种改变电阻器电阻的方法。首先，提供电阻器，其中电阻器具有长度L和电阻R1。电阻器的一部分暴露于激光辐射，其中该部分包括电阻器长度L的分数F. 在电阻器暴露于激光辐射之后，电阻器具有电阻R2，其中R2不等于R1。

87. 发明授权

US06645861B2 Self-aligned silicide process for silicon sidewall source and drain contacts 失效
标题翻译：用于硅侧壁源极和漏极触点的自对准硅化物工艺
公开(公告)号：US06645861B2
公开(公告)日：2003-11-11
申请号：US09836197
申请日：2001-04-18
申请人： Cyril Cabral, Jr. , Kevin K. Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Paul Michael Solomon , Ying Zhang
发明人： Cyril Cabral, Jr. , Kevin K. Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Paul Michael Solomon , Ying Zhang
IPC分类号： H01L2144
CPC分类号： H01L29/6653 , H01L21/28052 , H01L21/28518 , H01L29/41783 , H01L29/456 , H01L29/66507 , H01L29/66772 , H01L29/78618 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.
摘要翻译：在具有含硅区域的受控消耗的非平面含硅区域上形成金属硅化物接触的方法（以及由此形成的结构）包括在含硅区域上形成覆盖金属层，在金属上形成硅层层，相对于金属的硅层各向异性地选择性地蚀刻，在第一温度下使金属与硅反应以形成金属硅合金，蚀刻金属层的未反应部分，在第二温度退火以形成金属合金 -Si2，并且选择性地蚀刻未反应的硅层。

88. 发明授权

US06545339B2 Semiconductor device incorporating elements formed of refractory metal-silicon-nitrogen and method for fabrication 失效
$Semiconductor device incorporating elements formed of refractory metal-silicon-nitrogen and method for fabrication$
公开(公告)号：US06545339B2
公开(公告)日：2003-04-08
申请号：US09760245
申请日：2001-01-12
申请人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
发明人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
IPC分类号： H01L27108
CPC分类号： H01L21/76849 , H01L21/7687 , H01L21/76888 , H01L23/5258 , H01L27/0629 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure that includes at least one circuit element of a fuse, a diffusion barrier or a capacitor that is formed by refractory metal-silicon-nitrogen is disclosed. A method for fabricating such semiconductor structure that includes a fuse element, a diffusion barrier, a resistor or a capacitor by a refractory metal-silicon-nitrogen material is further disclosed. A suitable refractory metal-silicon-nitrogen material to be used is TaSiN which provides a wide range of resistivity by changing the ratio of Ta:Si:N. The invention provides the benefit that the various components of diffusion barriers, fuses, capacitors and resistors may be formed by a single deposition process of a TaSiN layer, the various components are then selectively masked and treated by either heat-treating or ion-implantation to vary their resistivity selectively while keeping the other shielded elements at the same resistivity.

89. 发明授权

US06503641B2 Interconnects with Ti-containing liners 有权
标题翻译：与含Ti衬板互连
公开(公告)号：US06503641B2
公开(公告)日：2003-01-07
申请号：US09740089
申请日：2000-12-18
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Chao-Kun Hu , Kim Yang Lee , Ismail Cevdet Noyan , Robert Rosenberg , Thomas McCarroll Shaw
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Chao-Kun Hu , Kim Yang Lee , Ismail Cevdet Noyan , Robert Rosenberg , Thomas McCarroll Shaw
IPC分类号： B32B1501
CPC分类号： H01L21/76843 , B32B15/01 , C22C27/02 , H01L21/76846 , H01L23/53223 , H01L23/53238 , H01L2924/0002 , Y10S428/929 , Y10S428/935 , Y10S428/936 , Y10S428/938 , Y10T428/12639 , Y10T428/12743 , Y10T428/12806 , Y10T428/12812 , Y10T428/12819 , Y10T428/12826 , Y10T428/12833 , Y10T428/1284 , Y10T428/12903 , H01L2924/00
摘要： An electrical conductor for use in an electronic structure is disclosed which includes a conductor body that is formed of an alloy including between about 0.001 atomic % and about 2 atomic % of an element selected from the group consisting of Ti, Zr, In, Sn and Hf; and a liner abutting the conductor body which is formed of an alloy that includes Ta, W, Ti, Nb and V. The invention further discloses a liner for use in a semiconductor interconnect that is formed of a material selected from the group consisting of Ti, Hf, In, Sn, Zr and alloys thereof, TiCu3, Ta1−XTix, Ta1−X, Hfx, Ta1−X, Inxy, Ta1−XSnx, Ta1−XZrx.
摘要翻译：公开了一种用于电子结构的电导体，其包括由合金构成的导体，该合金包括选自Ti，Zr，In，Sn中的元素的约0.001原子％至约2原子％，以及 Hf; 以及与包括Ta，W，Ti，Nb和V的合金形成的导体本体的衬垫。本发明还公开了一种用于半导体互连的衬垫，其由选自Ti ，Hf，In，Sn，Zr及其合金，TiCu3，Ta1-XTix，Ta1-X，Hfx，Ta1-X，Inxy，Ta1-XSnx，Ta1-XZrx。

90. 发明授权

US06291885B1 Thin metal barrier for electrical interconnections 失效
标题翻译：用于电互连的薄金属屏障
公开(公告)号：US06291885B1
公开(公告)日：2001-09-18
申请号：US08896925
申请日：1997-07-18
申请人： Cyril Cabral, Jr. , Patrick William DeHaven , Daniel Charles Edelstein , David Peter Klaus , James Manley Pollard, III , Carol L. Stanis , Cyprian Emeka Uzoh
发明人： Cyril Cabral, Jr. , Patrick William DeHaven , Daniel Charles Edelstein , David Peter Klaus , James Manley Pollard, III , Carol L. Stanis , Cyprian Emeka Uzoh
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/76843 , H01L23/53223 , H01L23/53233 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L24/11 , H01L24/12 , H01L29/4933 , H01L2224/05124 , H01L2224/05181 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10329 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/3025 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： An interconnect structure and barrier layer for electrical interconnections is described incorporating a layer of TaN in the hexagonal phase between a first material such as Cu and a second material such as Al, W, and PbSn. A multilayer of TaN in the hexagonal phase and Ta in the alpha phase is also described as a barrier layer. The invention overcomes the problem of Cu diffusion into materials desired to be isolated during temperature anneal at 500° C.
摘要翻译：描述了用于电互连的互连结构和阻挡层，其结合了诸如Cu的第一材料和诸如Al，W和PbSn的第二材料之间的六方相中的TaN层。六方相中的TaN多层和α相中的Ta也被描述为阻挡层。本发明克服了在500℃的温度退火期间将Cu扩散到期望分离的材料中的问题。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式