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81. 发明授权

US07200710B2 Buffer device and method of operation in a buffer device 失效
标题翻译：缓冲装置和缓冲装置中的操作方法
公开(公告)号：US07200710B2
公开(公告)日：2007-04-03
申请号：US11130734
申请日：2005-05-17
申请人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
发明人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
IPC分类号： G06F12/00
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012
摘要： An integrated circuit buffer device comprising a receiver circuit to receive control information and address information. A first interface portion provides at least a first control signal that specifies a write operation to a first memory device. The first control signal corresponds to the control information. A second interface portion provides a first address to the first memory device. The first address corresponds to the address information. The first address specifies a memory location for the write operation to the first memory device. A third interface portion provides a first signal to the first memory device. The first signal synchronizes communication of the first control signal from the integrated circuit buffer device to the first memory device. A fourth interface portion provides at least a second control signal that specifies a write operation to a second memory device. The second control signal corresponds to the control information. A fifth interface portion provides a second address to the second memory device. The second address corresponds to the address information. The second address specifies a memory location for the write operation to the second memory device. A sixth interface portion provides a second signal to the second memory device. The second signal synchronizes communication of the second control signal from the integrated circuit buffer device to the second memory device.
摘要翻译：一种集成电路缓冲器件，包括用于接收控制信息和地址信息的接收器电路。第一接口部分至少提供指定对第一存储器件的写入操作的第一控制信号。第一控制信号对应于控制信息。第二接口部分向第一存储器件提供第一地址。第一个地址对应于地址信息。第一个地址指定用于对第一个存储设备的写入操作的存储器位置。第三接口部分向第一存储器件提供第一信号。第一信号使来自集成电路缓冲器的第一控制信号与第一存储器件的通信同步。第四接口部分至少提供指定对第二存储器件的写入操作的第二控制信号。第二控制信号对应于控制信息。第五接口部分向第二存储器件提供第二地址。第二个地址对应于地址信息。第二地址指定用于对第二存储设备的写操作的存储器位置。第六接口部分向第二存储器件提供第二信号。第二信号使来自集成电路缓冲器的第二控制信号与第二存储器件的通信同步。

82. 发明授权

US07187572B2 Early read after write operation memory device, system and method 有权
标题翻译：写操作后早期读取存储器件，系统和方法
公开(公告)号：US07187572B2
公开(公告)日：2007-03-06
申请号：US10353405
申请日：2003-01-29
申请人： Richard E. Perego , Frederick A. Ware
发明人： Richard E. Perego , Frederick A. Ware
IPC分类号： G11C5/06 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C2207/2281 , G11C2207/229
摘要： A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment. The memory device includes an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.
摘要翻译：根据实施例，提供了在一个或多个写入操作之后允许早期读取操作的存储器件，系统和方法。存储器件包括用于提供第一写入地址，第一写入数据和读取地址的接口。存储器核心耦合到接口并且包括具有第一数据路径和第一地址路径的第一存储器部分和具有第二数据路径和第二地址路径的第二存储器部分。在本发明的实施例中，第一数据和第一地址路径独立于第二数据和第二地址路径。响应于在第一地址路径上提供第一写地址而在第一数据路径上提供第一写入数据，同时响应于在第二地址路径上提供的读地址在第二数据路径上提供读数据。

83. 发明授权

US06889304B2 Memory device supporting a dynamically configurable core organization 有权
公开(公告)号：US06889304B2
公开(公告)日：2005-05-03
申请号：US10302420
申请日：2002-11-22
申请人： Richard E. Perego , Donald C. Stark , Frederick A. Ware
发明人： Richard E. Perego , Donald C. Stark , Frederick A. Ware
IPC分类号： G06F12/04 , G06F12/06 , G11C5/00 , G11C5/04 , G11C7/10 , G11C8/00 , G11C11/408 , G11C11/4097 , H05K1/11 , H05K1/14 , G06F12/00 , G06F12/02
CPC分类号： G06F13/1678 , G06F12/04 , G06F12/06 , G06F12/0646 , G06F13/1657 , G06F13/4022 , G11C5/02 , G11C5/025 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1072 , G11C7/1087 , G11C8/06 , G11C11/4087 , G11C11/4097 , G11C2207/105 , G11C2207/108 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14
摘要： Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.

84. 发明授权

US06864896B2 Scalable unified memory architecture 有权
标题翻译：可扩展的统一内存架构
公开(公告)号：US06864896B2
公开(公告)日：2005-03-08
申请号：US09858836
申请日：2001-05-15
申请人： Richard E. Perego
发明人： Richard E. Perego
IPC分类号： G06T1/60 , G09G5/36 , G09G5/393 , G06F15/167
CPC分类号： G09G5/363 , G06T1/60 , G09G5/393 , G09G2352/00 , G09G2360/125
摘要： A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.
摘要翻译：存储器架构包括耦合到多个模块的存储器控制器。每个模块包括耦合到共享存储器的计算引擎。每个计算引擎能够从存储器控制器接收指令并处理接收到的指令。共享内存配置为存储主内存数据和图形数据。某些计算引擎能够处理图形数据。存储器控制器可以包括向计算引擎提供指令的图形控制器。每个模块上的互连允许多个模块耦合到存储器控制器。

85. 发明授权

US06359625B1 Video refresh compression 有权
标题翻译：视频刷新压缩
公开(公告)号：US06359625B1
公开(公告)日：2002-03-19
申请号：US09130509
申请日：1998-08-06
申请人： Richard E. Perego
发明人： Richard E. Perego
IPC分类号： G09G500
CPC分类号： G09G5/393 , G09G5/399 , G09G2340/02 , G09G2360/12 , G09G2360/125
摘要： A data compression apparatus and method of displaying graphics in a computer system employs a full frame buffer and compressed frame buffer wherein pixel data is sent to a display device and concurrently compressed and captured in parallel so that subsequent unchanged frames are regenerated directly from the compressed frame buffer.
摘要翻译：在计算机系统中显示图形的数据压缩装置和方法采用全帧缓冲器和压缩帧缓冲器，其中像素数据被发送到显示装置并且并行压缩和捕获，使得后续不变的帧直接从压缩帧重新生成缓冲。

86. 发明授权

US08924680B2 Memory controllers, systems, and methods supporting multiple request modes 有权
标题翻译：支持多种请求模式的内存控制器，系统和方法
公开(公告)号：US08924680B2
公开(公告)日：2014-12-30
申请号：US12745494
申请日：2008-04-11
申请人： Richard E. Perego , Frederick A. Ware
发明人： Richard E. Perego , Frederick A. Ware
IPC分类号： G06F13/00 , G06F13/28 , G11C7/10 , G06F13/16 , G11C5/06
CPC分类号： G11C7/1072 , G06F13/1678 , G06F13/1684 , G06F13/1694 , G11C5/06 , G11C7/1045 , G11C7/1075
摘要： A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.
摘要翻译：存储器系统包括具有多个存储器 - 控制器块的存储器控制器，每个存储器控制器块通过外部请求端口传送独立的事务请求。请求端口通过点对点连接耦合到一个到N个存储器件，每个存储器件包括N个可独立寻址的存储器块。所有外部请求端口都连接到存储设备上的相应外部请求端口或给定配置中使用的设备。每个存储器件的请求端口的数量和每个存储器件的数据宽度随着存储器件的数量而变化，使得请求访问粒度与数据粒度的比率保持恒定，而与存储器件的数量无关。

87. 发明授权

US08352772B2 Reference clock and command word alignment 有权
标题翻译：参考时钟和命令字对齐
公开(公告)号：US08352772B2
公开(公告)日：2013-01-08
申请号：US12598068
申请日：2008-05-08
申请人： Jade M. Kizer , Richard E. Perego
发明人： Jade M. Kizer , Richard E. Perego
IPC分类号： G06F1/04 , G06F1/14 , G06F11/00
CPC分类号： G11C7/22 , G11C7/222 , H03L7/0891 , H03L7/18
摘要： A memory system includes a memory controller that issues command signals and a reference-clock signal to a memory device. The edge rate of the reference-clock signal is lower than the bit rate of the command signals, so the memory device multiplies the reference clock signal to develop a command-recovery clock signal with which to sample the incoming command signals. The memory controller issues the command signals as a series of multi-bit command words aligned with edges of the reference-clock signal so that the memory device can use edges of the reference clock signal for command-word alignment.
摘要翻译：存储器系统包括向存储器件发出命令信号和参考时钟信号的存储器控制器。参考时钟信号的边沿速率低于命令信号的比特率，因此存储器件将参考时钟信号相乘以产生用于对输入的命令信号进行采样的命令恢复时钟信号。存储器控制器将命令信号发出为与参考时钟信号的边缘对准的一系列多位命令字，使得存储器件可以使用参考时钟信号的边沿进行命令字对准。

88. 发明申请

US20120182304A1 Scalable Unified Memory Architecture 审中-公开
标题翻译：可扩展的统一内存架构
公开(公告)号：US20120182304A1
公开(公告)日：2012-07-19
申请号：US13430405
申请日：2012-03-26
申请人： Richard E. Perego
发明人： Richard E. Perego
IPC分类号： G06F15/167
CPC分类号： G09G5/363 , G06T1/60 , G09G5/393 , G09G2352/00 , G09G2360/125
摘要： A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.
摘要翻译：存储器架构包括耦合到多个模块的存储器控制器。每个模块包括耦合到共享存储器的计算引擎。每个计算引擎能够从存储器控制器接收指令并处理接收到的指令。共享内存配置为存储主内存数据和图形数据。某些计算引擎能够处理图形数据。存储器控制器可以包括向计算引擎提供指令的图形控制器。每个模块上的互连允许多个模块耦合到存储器控制器。

89. 发明申请

US20110219197A1 Memory Controllers, Systems, and Methods Supporting Multiple Request Modes 有权
标题翻译：支持多种请求模式的内存控制器，系统和方法
公开(公告)号：US20110219197A1
公开(公告)日：2011-09-08
申请号：US12745494
申请日：2008-04-11
申请人： Richard E. Perego , Frederick A. Ware
发明人： Richard E. Perego , Frederick A. Ware
IPC分类号： G06F12/00
CPC分类号： G11C7/1072 , G06F13/1678 , G06F13/1684 , G06F13/1694 , G11C5/06 , G11C7/1045 , G11C7/1075
摘要： A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.
摘要翻译：存储器系统包括具有多个存储器 - 控制器块的存储器控制器，每个存储器控制器块通过外部请求端口传送独立的事务请求。请求端口通过点对点连接耦合到一个到N个存储器件，每个存储器件包括N个可独立寻址的存储器块。所有外部请求端口都连接到存储设备上的相应外部请求端口或给定配置中使用的设备。每个存储器件的请求端口的数量和每个存储器件的数据宽度随着存储器件的数量而变化，使得请求访问粒度与数据粒度的比率保持恒定，而与存储器件的数量无关。

90. 发明授权

US07821519B2 Scalable unified memory architecture 有权
标题翻译：可扩展的统一内存架构
公开(公告)号：US07821519B2
公开(公告)日：2010-10-26
申请号：US11058051
申请日：2005-02-15
申请人： Richard E. Perego
发明人： Richard E. Perego
IPC分类号： G06F15/167 , G06F13/14 , G06F15/80
CPC分类号： G09G5/363 , G06T1/60 , G09G5/393 , G09G2352/00 , G09G2360/125
摘要： A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.
摘要翻译：存储器架构包括耦合到多个模块的存储器控制器。每个模块包括耦合到共享存储器的计算引擎。每个计算引擎能够从存储器控制器接收指令并处理接收到的指令。共享内存配置为存储主内存数据和图形数据。某些计算引擎能够处理图形数据。存储器控制器可以包括向计算引擎提供指令的图形控制器。每个模块上的互连允许多个模块耦合到存储器控制器。

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