专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US07580280B2 Method and apparatus for a non-volatile memory device with reduced program disturb 有权
标题翻译：减少程序干扰的非易失性存储器件的方法和装置
公开(公告)号：US07580280B2
公开(公告)日：2009-08-25
申请号：US11862903
申请日：2007-09-27
申请人： Chung-Kuang Chen
发明人： Chung-Kuang Chen
IPC分类号： G11C16/24
CPC分类号： G11C5/14 , G11C7/12 , G11C16/0491 , G11C16/24 , G11C16/3427
摘要： A non-volatile memory device includes a plurality of power control circuits interfaced via a single Y multiplexer with an array of memory cells. The multiple power control circuits provide multiple pre-charge paths configured to pre-charge the drain node of a target memory cell in the array, as well as the drain and/or source nodes of unselected memory cells in the array. The multiple pre-charge paths decrease the current through the array cells and also decrease the pre-charge and set up times for the array.
摘要翻译：非易失性存储器件包括经由单个Y复用器与存储器单元阵列接口的多个功率控制电路。多个功率控制电路提供多个预充电路径，其被配置为对阵列中的目标存储器单元的漏极节点以及阵列中未选择的存储器单元的漏极和/或源节点进行预充电。多个预充电路径减少了通过阵列单元的电流，并且还减少了阵列的预充电和设置时间。

82. 发明申请

US20090128115A1 VOLTAGE REGULATOR AND CONTROLLING METHOD THEREOF 有权
标题翻译：电压调节器及其控制方法
公开(公告)号：US20090128115A1
公开(公告)日：2009-05-21
申请号：US11940368
申请日：2007-11-15
申请人： Chung-Kuang Chen , Chun-Shiung Hung , Yi-Te Shih
发明人： Chung-Kuang Chen , Chun-Shiung Hung , Yi-Te Shih
IPC分类号： G05F1/44 , G05F1/10
CPC分类号： G05F1/56
摘要： A controlling method of a voltage regulator is provided. The voltage regulator at least includes a differential circuit and a pump high-voltage circuit which has a bias path, an output transistor and an output terminal. The controlling method includes steps of: providing at least a pre-charge path to the pump high-voltage circuit, closing the bias path and charging the output terminal with the pre-charge path when the output terminal is transient, detecting an output level of the output terminal, and closing the pre-charge path and open the bias path to bias the output transistor when the output level reaches a predetermined value.
摘要翻译：提供了一种电压调节器的控制方法。电压调节器至少包括差分电路和具有偏置路径的输出晶体管和输出端子的泵高压电路。所述控制方法包括以下步骤：在所述泵高压电路至少提供预充电路径时，当所述输出端子为瞬态时，关闭所述偏置通路并对所述输出端子充电所述预充电路径，检测所述输出端子的输出电平输出端子，并且当输出电平达到预定值时，闭合预充电路径并打开偏置通路以偏置输出晶体管。

83. 发明授权

US07391672B1 Sequential memory and accessing method thereof 有权
标题翻译：顺序存储器及其访问方法
公开(公告)号：US07391672B1
公开(公告)日：2008-06-24
申请号：US11645708
申请日：2006-12-27
申请人： Chang-Ting Chen , Chung-Kuang Chen
发明人： Chang-Ting Chen , Chung-Kuang Chen
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/1018 , G11C16/0491 , G11C16/26 , G11C17/126 , G11C2207/005
摘要： A method for accessing a memory sequentially. The memory has (m+1) bit lines and at least one row of transistors, wherein m is a positive integer. This method includes the following steps. First, voltage levels of first and second terminals of the transistors are equalized to a ground voltage in a pre-discharge period. Next, the voltage levels of the first and second terminals of the nth transistor are respectively transformed into a source voltage and a drain voltage in an nth reading period, and the voltage level of the second terminal of the (n+1)th transistor is transformed into an isolation voltage, wherein n is a positive integer smaller than m. Thereafter, the voltage levels of the first and second terminals of the mth transistor are respectively transformed into the source voltage and the drain voltage in an mth reading period. The source voltage equals the ground voltage.
摘要翻译：一种顺序访问存储器的方法。存储器具有（m + 1）位线和至少一行晶体管，其中m是正整数。该方法包括以下步骤。首先，晶体管的第一和第二端子的电压电平在预放电时段内与地电压相等。接下来，第n 晶体管的第一端子和第二端子的电压电平分别在第n 读取周期中变换为源极电压和漏极电压，并且（n + 1）^{晶体管的第二端子的电压电平变换为隔离电压，其中n是小于m的正整数。此后，在第m个读取周期中，第m个/或者以上晶体管的第一和第二端子的电压电平分别变换为源极电压和漏极电压。源极电压等于接地电压。}

84. 发明申请

US20080025102A1 METHOD FOR MEMORY DATA STORAGE BY PARTITION INTO NARROWER THRESHOLD VOLTAGE DISTRIBUTION REGIONS 有权
标题翻译：用于存储数据存储的方法，通过分段到低电压电压分配区域
公开(公告)号：US20080025102A1
公开(公告)日：2008-01-31
申请号：US11460483
申请日：2006-07-27
申请人： Chung-Kuang Chen , Ful-Long Ni
发明人： Chung-Kuang Chen , Ful-Long Ni
IPC分类号： G11C16/04
CPC分类号： G11C16/3454 , G11C11/5628 , G11C2211/5621 , G11C2211/5634
摘要： A method for data storage of a memory unit and a memory unit using the same are provided in the present invention. The method for data storage of a memory unit includes: first, dividing a memory unit into a plurality of small memory groups; next, defining a threshold voltage distribution region for each small memory group; then, defining a plurality of program verify threshold voltages and a plurality of reference detecting values for each small memory group according to the threshold voltage distribution region of each small memory group; and after that, using these small memory groups to store data.
摘要翻译：在本发明中提供了一种存储单元和使用其的存储单元的数据存储方法。存储单元的数据存储方法包括：首先，将存储器单元划分成多个小存储器组; 接下来，为每个小存储器组定义阈值电压分布区域; 然后根据每个小存储器组的阈值电压分布区域为每个小存储器组定义多个程序验证阈值电压和多个参考检测值; 之后，使用这些小内存组来存储数据。

85. 发明申请

US20070070744A1 Fast pre-charge circuit and method of providing same for memory devices 有权
标题翻译：快速预充电电路及其为存储器件提供相同的方法
公开(公告)号：US20070070744A1
公开(公告)日：2007-03-29
申请号：US11236347
申请日：2005-09-27
申请人： Chung-Kuang Chen
发明人： Chung-Kuang Chen
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C8/08 , G11C2207/2254
摘要： A fast pre-charge circuit and method of providing a fast pre-charge for an integrated circuit memory device is disclosed. The fast pre-charge circuit comprises an address calculating unit and a multi-power driver. The address calculating unit detects the sector distance from driver of the integrated circuit memory device, and the driver provides a voltage to the loading of the integrated circuit memory device based on an output of the address calculating unit. Unlike a conventional fixed-power wordline driver, the driver of the present invention provides multiple voltage levels to the wordline or dynamically adjusts for different loading situations.
摘要翻译：公开了一种为集成电路存储器件提供快速预充电的快速预充电电路和方法。快速预充电电路包括地址计算单元和多功率驱动器。地址计算单元检测与集成电路存储器件的驱动器的扇区距离，并且驱动器基于地址计算单元的输出向集成电路存储器件的加载提供电压。与传统的固定功率字线驱动器不同，本发明的驱动器向字线提供多个电压电平或者针对不同的负载情况动态调整。

86. 发明授权

US06980456B2 Memory with low and fixed pre-charge loading 有权
标题翻译：内存低，固定预充电负载
公开(公告)号：US06980456B2
公开(公告)日：2005-12-27
申请号：US10794048
申请日：2004-03-08
申请人： Chung-Kuang Chen , Hsiang-Pang Li
发明人： Chung-Kuang Chen , Hsiang-Pang Li
IPC分类号： G11C5/06 , G11C5/14 , G11C7/00 , G11C17/00
CPC分类号： G11C16/0491 , G11C5/063 , G11C7/12 , G11C16/26
摘要： A virtual ground memory with low and fixed pre-charge loading is provided. First metal lines GL(n−1), GL(n), and GL(n+1) and second metal lines BL(n−1) and BL(n) are disposed in the sequence GL(n−1), BL(n−1), GL(n), BL(n) and GL(n+1). Each first metal line and the adjacent second metal line are coupled respectively to two ends of the corresponding memory cell. Word lines are used for controlling memory cells. The second metal lines BL are in high level when the memory cells which the second metal lines BL are coupled to are chosen. A first and second sense amplifier are coupled to the second metal line BL(n−1) and BL(n) respectively, and the first metal lines GL(n−1) and GL(n+1) are coupled to ground level. One of the word lines is enabled to read the corresponding memory cells. A virtual ground memory loading can be fixed by this invention.
摘要翻译：提供具有低和固定预充电负载的虚拟接地存储器。第一金属线GL（n-1），GL（n）和GL（n + 1）和第二金属线BL（n-1）和BL（n）（n-1），GL（n），BL（n）和GL（n + 1）。每个第一金属线和相邻的第二金属线分别耦合到相应存储单元的两端。字线用于控制存储单元。当选择第二金属线BL耦合到的存储单元时，第二金属线BL处于高电平。第一和第二读出放大器分别耦合到第二金属线BL（n-1）和BL（n），并且第一金属线GL（n-1）和GL（n + 1）被耦合到地电平。其中一条字线能够读取相应的存储单元。虚拟地面存储器加载可以通过本发明来修复。

87. 发明授权

US08386884B2 Memory apparatus with multi-level cells and operation method thereof 有权
标题翻译：具有多级单元的存储装置及其操作方法
公开(公告)号：US08386884B2
公开(公告)日：2013-02-26
申请号：US12502353
申请日：2009-07-14
申请人： Chung-Kuang Chen
发明人： Chung-Kuang Chen
IPC分类号： G11C29/00 , G11C11/34
CPC分类号： G11C11/5621 , G06F11/1072 , G11C16/34
摘要： A memory apparatus and an operation method thereof are provided. The memory apparatus includes a plurality of multi-level cells and a controller. The controller encodes input data according to a target encoding code to generate a plurality of encoded subsets, and stores the encoded subsets into the multi-level cells. Thereafter, the controller could read data from the multi-level cells, perform an error correction procedure on the read data to correct and recover the read data as recovered data, and decode the recovered data according to the target encoding code. Consequently, sensing windows between threshold voltage distributions of the multi-level cells are expanded.
摘要翻译：提供了一种存储装置及其操作方法。存储装置包括多个多电平单元和控制器。控制器根据目标编码代码对输入数据进行编码以生成多个编码子集，并将经编码的子集存储到多级单元中。此后，控制器可以从多电平单元读取数据，对读取的数据执行纠错过程，以校正并恢复读取的数据作为恢复的数据，并根据目标编码代码解码恢复的数据。因此，扩展了多级单元的阈值电压分布之间的感测窗口。

88. 发明申请

US20110291638A1 Clock Integrated Circuit 有权
标题翻译：时钟集成电路
公开(公告)号：US20110291638A1
公开(公告)日：2011-12-01
申请号：US12834369
申请日：2010-07-12
申请人： Chung-Kuang Chen
发明人： Chung-Kuang Chen
IPC分类号： G05F3/02
CPC分类号： H03K3/012 , H03K3/011 , H03K3/013 , H03K3/0231
摘要： The clock circuit of an integrated circuit operates with tolerance of variation in power. A compensation circuit is powered by a supply voltage. The compensation circuit generates a compensated voltage reference, which is compensated for variation in the supply voltage. The compensated voltage reference is compared by comparison circuitry against an output of timing circuitry, to determine timing of the clock signal.
摘要翻译：集成电路的时钟电路具有功率变化容限。补偿电路由电源供电。补偿电路产生补偿电压基准，补偿电压参考电压补偿电压变化。补偿电压基准通过比较电路与定时电路的输出进行比较，以确定时钟信号的时序。

89. 发明申请

US20080159060A1 SEQUENTIAL MEMORY AND ACCESSING METHOD THEREOF 有权
标题翻译：顺序存储器及其访问方法
公开(公告)号：US20080159060A1
公开(公告)日：2008-07-03
申请号：US11645708
申请日：2006-12-27
申请人： Chang-Ting Chen , Chung-Kuang Chen
发明人： Chang-Ting Chen , Chung-Kuang Chen
IPC分类号： G11C8/00
CPC分类号： G11C7/12 , G11C7/1018 , G11C16/0491 , G11C16/26 , G11C17/126 , G11C2207/005
摘要： A method for accessing a memory sequentially. The memory has (m+1) bit lines and at least one row of transistors, wherein m is a positive integer. This method includes the following steps. First, voltage levels of first and second terminals of the transistors are equalized to a ground voltage in a pre-discharge period. Next, the voltage levels of the first and second terminals of the nth transistor are respectively transformed into a source voltage and a drain voltage in an nth reading period, and the voltage level of the second terminal of the (n+1)th transistor is transformed into an isolation voltage, wherein n is a positive integer smaller than m. Thereafter, the voltage levels of the first and second terminals of the mth transistor are respectively transformed into the source voltage and the drain voltage in an mth reading period. The source voltage equals the ground voltage.
摘要翻译：一种顺序访问存储器的方法。存储器具有（m + 1）位线和至少一行晶体管，其中m是正整数。该方法包括以下步骤。首先，晶体管的第一和第二端子的电压电平在预放电时段内与地电压相等。接下来，第n 晶体管的第一端子和第二端子的电压电平分别在第n 读取周期中变换为源极电压和漏极电压，并且将第（n + 1）个第晶体管的第二端子的电压电平变换为隔离电压，其中n是小于m的正整数。此后，在第m个读取周期中，第m个/或者以上晶体管的第一和第二端子的电压电平分别变换为源极电压和漏极电压。源极电压等于接地电压。

90. 发明授权

US07313018B2 Methods and apparatus for a non-volatile memory device with reduced program disturb 有权
标题翻译：减少程序干扰的非易失性存储器件的方法和装置
公开(公告)号：US07313018B2
公开(公告)日：2007-12-25
申请号：US11370368
申请日：2006-03-08
申请人： Chung-Kuang Chen
发明人： Chung-Kuang Chen
IPC分类号： G11C16/30
CPC分类号： G11C5/14 , G11C7/12 , G11C16/0491 , G11C16/24 , G11C16/3427
摘要： A non-volatile memory device includes a plurality of power control circuits interfaced via a single Y multiplexer with an array of memory cells. The multiple power control circuits provide multiple pre-charge paths configured to pre-charge the drain node of a target memory cell in the array, as well as the drain and/or source nodes of unselected memory cells in the array. The multiple pre-charge paths decrease the current through the array cells and also decrease the pre-charge and set up times for the array.
摘要翻译：非易失性存储器件包括经由单个Y复用器与存储器单元阵列接口的多个功率控制电路。多个功率控制电路提供多个预充电路径，其被配置为对阵列中的目标存储器单元的漏极节点以及阵列中未选择的存储器单元的漏极和/或源节点进行预充电。多个预充电路径减少了通过阵列单元的电流，并且还减少了阵列的预充电和设置时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式