专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US07461117B2 Floating point unit with fused multiply add and method for calculating a result with a floating point unit 失效
标题翻译：具有融合乘法的浮点单元和用浮点单元计算结果的方法
公开(公告)号：US07461117B2
公开(公告)日：2008-12-02
申请号：US11055812
申请日：2005-02-11
申请人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
发明人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/5443
摘要： The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of the alignment logic (3) output have all the same value in order to: a) control the carry logic of the adder logic (5) and/or b) control a stage of the normalization logic (6).
摘要翻译：本发明提出了一种具有融合乘法运算的浮点单元（1），具有一个加数运算数（eb，fb）和两个被乘数运算符（ea，fa; ec，fc），其中移位量逻辑（2）基于操作数（ea，eb和ec）的指数利用对准逻辑（3）计算对准偏移量，该对准逻辑（3）使用对准移位量来对齐加数操作数的分数（fb）与乘法逻辑（4）将乘法器操作数（fa，fc）的分数与加法器逻辑（5）相乘，该逻辑（5）将对准逻辑（3）和乘法逻辑（4）的输出与归一化逻辑（6）进行归一化，归一化逻辑（6）加法器逻辑（5）的特征在于提供一个前导零逻辑（7），其计算加法运算数（fb）的分数的前导零的数量，并且提供比较逻辑（8）其基于前导零的数量和对准偏移量计算指示mo的选择信号对准逻辑（3）输出的高有效位具有全部相同的值，以便：a）控制加法器逻辑（5）的进位逻辑和/或b）控制归一化逻辑（6）的阶段。

82. 发明申请

US20080092096A1 METHOD AND SYSTEM FOR OPTIMIZED AUTOMATED CASE-SPLITTING VIA CONSTRAINTS IN A SYMBOLIC SIMULATION FRAMEWORK 审中-公开
标题翻译：通过符号模拟框架中的约束优化自动分割的方法和系统
公开(公告)号：US20080092096A1
公开(公告)日：2008-04-17
申请号：US11954626
申请日：2007-12-12
申请人： JASON BAUMGARTNER , Christian Jacobi , Viresh Paruthi , Kai Weber
发明人： JASON BAUMGARTNER , Christian Jacobi , Viresh Paruthi , Kai Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for performing verification is proposed. The method comprises receiving a design and building an intermediate binary decision diagram for the design containing one or more nodal binary decision diagrams. In response to a size of the intermediate binary decision diagram exceeding a size threshold, a node of the design is selected for case-splitting. A first case-splitting is performed upon the selected node of the design to generate a primary constraint for setting the selected node to a primary value. A first constraining is performed on one of the one or more nodal binary decision diagrams with the primary constraint to generate a primary final binary decision diagram, a first verification of the design is performed using the primary final binary decision diagram.
摘要翻译：提出了一种执行验证的方法。该方法包括接收设计并构建用于包含一个或多个节点二进制决策图的设计的中间二进制决策图。响应于超过尺寸阈值的中间二进制判定图的大小，设计的节点被选择用于案例分割。在设计的所选节点上执行第一个案例分解，以生成将所选节点设置为主值的主约束。在具有主要约束的一个或多个节点二进制决策图中的一个上执行第一约束以生成主要的最终二进制决策图，使用主要的最终二进制决策图来执行设计的第一次验证。

83. 发明授权

US07302656B2 Method and system for performing functional verification of logic circuits 失效
标题翻译：用于执行逻辑电路功能验证的方法和系统
公开(公告)号：US07302656B2
公开(公告)日：2007-11-27
申请号：US11385928
申请日：2006-03-21
申请人： Kai Weber , Christian Jacobi , Nico Gulden , Viresh Paruthi , Klaus Keuerleber
发明人： Kai Weber , Christian Jacobi , Nico Gulden , Viresh Paruthi , Klaus Keuerleber
IPC分类号： G06F9/45
CPC分类号： G06F17/504
摘要： A method, a computer program product and a system for performing functional verification logic circuits. The invention enables the functional formal verification of a hardware logic design by replacing the parts that cannot be formally verified easily. In one form the invention is applied to a logic design including a multiplier circuit. The multiplier is replaced (51) by pseudo inputs. The input signal values of the multiplier circuit are determined (54) automatically from a counterexample (53) delivered (52) by a functional formal verification system for a modified design where the multiplier is replaced by pseudo signals. The input signal values are combined (55) with other known inputs to form a test case (56) file that can be used by a logic simulator to analyse the counterexample (52) on the unmodified hardware design including the multiplier.
摘要翻译：一种用于执行功能验证逻辑电路的方法，计算机程序产品和系统。本发明通过更换不能被正式验证的部件容易地实现对硬件逻辑设计的功能形式验证。在一种形式中，本发明应用于包括乘法器电路的逻辑设计。乘法器被伪输入替换（51）。乘法器电路的输入信号值通过功能形式验证系统自动地从通过伪信号代替乘法器的修改设计的函数形式验证系统（52）自动地从反例（53）中确定（54）。输入信号值与其他已知输入组合（55）以形成测试用例（56）文件，该文件可被逻辑模拟器用于在包括乘数的未修改的硬件设计上分析反例（52）。

84. 发明授权

US07245159B2 Protecting one-hot logic against short-circuits during power-on 失效
标题翻译：保护开机时防止短路的单热逻辑
公开(公告)号：US07245159B2
公开(公告)日：2007-07-17
申请号：US10891771
申请日：2004-07-15
申请人： Sang Hoo Dhong , Christian Jacobi , Hwa-Joon Oh , Silvia Melitta Mueller
发明人： Sang Hoo Dhong , Christian Jacobi , Hwa-Joon Oh , Silvia Melitta Mueller
IPC分类号： H03K19/20
CPC分类号： H03K17/223 , H03K17/005
摘要： A method, a computer program, and an apparatus are provided to protect transmission gates in a multiplexer (mux). Because transmission gates are much faster than the more convention AND-OR arrays, transmission gate usage in muxes are being used more often in high speed circuitry. However, transmission gate have a significant problem in that short circuit are possible for situations where there is not a one-hot select signal. Therefore, to eliminate the problem, logic gates are utilized specifically during Power-On Reset (POR) to force a one-hot selection to prevent any possible short circuits.
摘要翻译：提供了一种方法，计算机程序和装置来保护复用器（多路复用器）中的传输门。因为传输门比更常规的AND-OR阵列快得多，所以在高速电路中更频繁地使用多路复用器中的传输门使用。然而，传输门具有显着的问题，即在没有单热选择信号的情况下短路是可能的。因此，为了消除这个问题，在上电复位（POR）期间特别使用逻辑门来强制单热选择以防止任何可能的短路。

85. 发明申请

US20070061765A1 Method and system for case-splitting on nodes in a symbolic simulation framework 有权
标题翻译：符号仿真框架中节点分割的方法和系统
公开(公告)号：US20070061765A1
公开(公告)日：2007-03-15
申请号：US11225651
申请日：2005-09-13
申请人： Christian Jacobi , Geert Janssen , Viresh Paruthi , Kai Weber
发明人： Christian Jacobi , Geert Janssen , Viresh Paruthi , Kai Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variable from among the one or more variables represented by the one or more nodes by setting the first fattest variable to a primary value, and a first cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using an inverse of the primary value to generate a first cofactored binary decision diagram set. A second cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using the primary value to generate a second cofactored binary decision diagram set, and verification of the design is performed by evaluating a property of the second cofactored binary decision diagram set.
摘要翻译：用于执行验证的方法包括：为设计接收设计和构建包含表示一个或多个变量的一个或多个节点的中间二进制判定图集。通过将第一个胖子变量设置为一个初始值，对由一个或多个节点表示的一个或多个变量中的第一个胖子变量执行第一个分解，并且对该中间二进制判定图集执行第一个共同构想相对于使用主值的逆的一个或多个节点来生成第一辅因子二进制决策图集。对相对于一个或多个节点设置的中间二进制判定图，使用主值来生成第二共有二元决策图集，执行第二共同构想，并且通过评估第二构成二进制的属性来执行设计的验证决策图集。

86. 发明申请

US20060294481A1 Method and system for optimized automated case-splitting via constraints in a symbolic simulation framework 失效
标题翻译：用于通过符号仿真框架中的约束优化自动案例分解的方法和系统
公开(公告)号：US20060294481A1
公开(公告)日：2006-12-28
申请号：US11165455
申请日：2005-06-23
申请人： Jason Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Weber
发明人： Jason Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for performing verification is proposed. The method comprises receiving a design and building an intermediate binary decision diagram for the design containing one or more nodal binary decision diagrams. In response to a size of the intermediate binary decision diagram exceeding a size threshold, a node of the design is selected for case-splitting. A first case-splitting is performed upon the selected node of the design to generate a primary constraint for setting the selected node to a primary value. A first constraining is performed on one of the one or more nodal binary decision diagrams with the primary constraint to generate a primary final binary decision diagram, a first verification of the design is performed using the primary final binary decision diagram.
摘要翻译：提出了一种执行验证的方法。该方法包括接收设计并构建用于包含一个或多个节点二进制决策图的设计的中间二进制决策图。响应于超过尺寸阈值的中间二进制判定图的大小，设计的节点被选择用于案例分割。在设计的所选节点上执行第一个案例分解，以生成将所选节点设置为主值的主约束。在具有主要约束的一个或多个节点二进制决策图中的一个上执行第一约束以生成主要的最终二进制决策图，使用主要的最终二进制决策图来执行设计的第一次验证。

87. 发明申请

US20060190868A1 Method and system for optimized handling of constraints during symbolic simulation 有权
标题翻译：在符号仿真期间优化处理约束的方法和系统
公开(公告)号：US20060190868A1
公开(公告)日：2006-08-24
申请号：US11050592
申请日：2005-02-03
申请人： Jason Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Weber
发明人： Jason Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for verifying a design through symbolic simulation is disclosed. The method comprises creating one or more binary decision diagram variables for one or more inputs in a design containing one or more state variables and building a binary decision diagram for a first node of one or more nodes of the design. A binary decision diagram for the initial state function of one or more state variables of the design is generated and the design is subsequently initialized. Binary decisions diagrams for one or more constraints are synthesized. A set of constraint values is accumulated over time by combining the binary decision diagrams for the one or more constraints with a set of previously generated binary decision diagrams for a set of constraints previously used in one or more previous time-steps. A binary decision diagram for the next state function of the one or more state variables in the design is constructed in the presence of the constraints. The one or more state variables in the design are updated by propagating the binary decision diagram for the next state function to the one or more state variables and a set of binary decision diagrams for the one or more targets in the presence of the one or more constraints is calculated. The set of binary decision diagrams for one or more targets is constrained and the design is verified by determining whether the one or more targets were hit.
摘要翻译：公开了一种通过符号仿真验证设计的方法。该方法包括为包含一个或多个状态变量的设计中的一个或多个输入创建一个或多个二进制决策图变量，以及为设计的一个或多个节点的第一节点构建二进制决策图。生成设计的一个或多个状态变量的初始状态函数的二进制决策图，随后初始化设计。合成一个或多个约束的二进制决策图。通过将一个或多个约束的二进制判定图与先前在一个或多个先前时间步骤中使用的一组约束的先前生成的二进制决策图的组合来累积一组约束值。设计中一个或多个状态变量的下一个状态函数的二进制决策图是在有约束的情况下构建的。设计中的一个或多个状态变量通过将下一个状态函数的二进制决策图传播到一个或多个状态变量和一个或多个目标的存在下的一个或多个目标的一组二进制决策图来更新计算约束。用于一个或多个目标的二进制决策图集被约束，并且通过确定一个或多个目标是否被击中来验证设计。

88. 发明申请

US20060101107A1 Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units 失效
标题翻译：用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置
公开(公告)号：US20060101107A1
公开(公告)日：2006-05-11
申请号：US10982110
申请日：2004-11-05
申请人： Sang Dhong , Harm Hofstee , Christian Jacobi , Silvia Mueller , Hwa-Joon Oh
发明人： Sang Dhong , Harm Hofstee , Christian Jacobi , Silvia Mueller , Hwa-Joon Oh
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： An apparatus for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译：公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

89. 发明申请

US20060047680A1 Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit 有权
标题翻译：在数字电路的结构网络表示中有效构建二进制决策图的方法和系统
公开(公告)号：US20060047680A1
公开(公告)日：2006-03-02
申请号：US10926587
申请日：2004-08-26
申请人： Viresh Paruthi , Christian Jacobi , Geert Janssen , Jiazhao Xu , Kai Weber
发明人： Viresh Paruthi , Christian Jacobi , Geert Janssen , Jiazhao Xu , Kai Weber
IPC分类号： G06F7/00
CPC分类号： G06F17/30958 , G06F17/504 , Y10S707/99942
摘要： A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached. In response to determining that a union of first set and the second set of m-ary decision representations do not describe the logic function, the first and second size limits are increased, and the steps of building the first and second set are repeated. In response to determining that the union of the first set of m-ary decision representations and the second set of m-ary decision representations describe the logic function, the union is reported.
摘要翻译：公开了一种用于使用动态资源约束和交错深度优先搜索和修改的宽度优先搜索时间表在数字电路的结构网络表示中有效地构建决策图的方法，系统和计算机程序产品。该方法包括：对描述逻辑功能的一个或多个多元决策表示的第一集合设置第一大小限制，并为描述逻辑功能的一个或多个虚拟决策表示的第二组设置第二大小限制。然后，利用深度优先技术或宽度优先技术的集合之一构建逻辑功能的第一组m元决定表示，直到达到第一大小限制，并且第二组m元决定使用其他技术构建逻辑功能的表示，直到达到第二个大小限制。响应于确定第一集合和第二组m元决定表示的并集不描述逻辑函数，增加第一和第二大小限制，并且重复构建第一集合和第二集合的步骤。响应于确定第一组m元决策表示和第二组m元决策表示的并集描述逻辑函数，报告联合。

90. 发明申请

US20060026223A1 Apparatus and method for reducing the latency of sum-addressed shifters 有权
标题翻译：用于减少和寻址移位器的延迟的装置和方法
公开(公告)号：US20060026223A1
公开(公告)日：2006-02-02
申请号：US10902475
申请日：2004-07-29
申请人： Sang Dhong , Christian Jacobi , Silvia Mueller , Hiroo Nishikawa , Hwa-Joon Oh
发明人： Sang Dhong , Christian Jacobi , Silvia Mueller , Hiroo Nishikawa , Hwa-Joon Oh
IPC分类号： G06F7/00
CPC分类号： G06F5/012
摘要： The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.
摘要翻译：本发明提供了作为多个数字的函数的移位量的计算。至少一个解码器和至少一个加法器并联耦合。移位器被配置为计算多个移位级中的值，并且其中移位量的位组可用于影响多个移位级中的至少一个，从而减少处理时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式