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81. 发明授权

US06413857B1 Method of creating ground to avoid charging in SOI products 有权
标题翻译：创建地面以避免在SOI产品中充电的方法
公开(公告)号：US06413857B1
公开(公告)日：2002-07-02
申请号：US09824349
申请日：2001-04-02
申请人： Ramkumar Subramanian , Bharath Rangarajan , Bhanwar Singh
发明人： Ramkumar Subramanian , Bharath Rangarajan , Bhanwar Singh
IPC分类号： H01L214763
CPC分类号： H01L29/66772 , H01L21/743 , H01L21/84 , H01L29/78612 , H01L29/78645 , H01L29/78648
摘要： An SOI device structure is provided which facilitates mitigation of charge build up caused by floating body effects. A plurality of local interconnects are formed from a top insulating layer to a top silicon layer of the SOI device structure. A ground contact is then formed from the top insulating layer to a bottom substrate layer of the SOI device structure. The ground contact extends through the insulating layer, an isolation region and an oxide layer to the bottom substrate layer.
摘要翻译：提供了SOI器件结构，其有助于减轻由浮体效应引起的电荷积累。多个局部互连由SOI器件结构的顶部绝缘层到顶部硅层形成。然后从顶部绝缘层到SOI器件结构的底部基底层形成接地触点。接地触头延伸穿过绝缘层，隔离区域和氧化物层延伸到底部基底层。

82. 发明授权

US06326231B1 Use of silicon oxynitride ARC for metal layers 有权
标题翻译：氧氮化硅ARC用于金属层
公开(公告)号：US06326231B1
公开(公告)日：2001-12-04
申请号：US09207562
申请日：1998-12-08
申请人： Ramkumar Subramanian , Bhanwar Singh , Sanjay K. Yedur , Marina V. Plat , Christopher F. Lyons , Bharath Rangarajan , Michael K. Templeton
发明人： Ramkumar Subramanian , Bhanwar Singh , Sanjay K. Yedur , Marina V. Plat , Christopher F. Lyons , Bharath Rangarajan , Michael K. Templeton
IPC分类号： H01L2100
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/3143 , H01L21/3145
摘要： In one embodiment, the present invention relates to a method of forming a silicon oxynitride antireflection coating over a metal layer, involving the steps of providing a semiconductor substrate comprising the metal layer over at least part of the semiconductor substrate; depositing a silicon oxynitride layer over the metal layer having a thickness from about 100 Å to about 150 Å; and forming an oxide layer having a thickness from about 5 Å to about 50 Å over the silicon oxynitride layer to provide the silicon oxynitride antireflection coating. In another embodiment, the present invention relates to a method of reducing an apparent reflectivity of a metal layer having a first reflectivity in a semiconductor structure, involing forming a silicon oxynitride antireflection coating over the metal layer; wherein the silicon oxynitride antireflection coating formed over the metal layer has a second reflectivity and is formed by depositing silicon oxynitride on the metal layer by chemical vapor deposition and forming an oxide layer over the oxynitride, and the difference between the first reflectivity and the second reflectivity is at least about 60%.
摘要翻译：在一个实施方案中，本发明涉及在金属层上形成氮氧化硅抗反射涂层的方法，包括以下步骤：在半导体衬底的至少一部分上提供包括金属层的半导体衬底; 在所述金属层上沉积厚度为约至约的氧氮化硅层; 并在氮氧化硅层上形成厚度约为5-20埃的氧化物层，以提供氮氧化硅抗反射涂层。在另一个实施方案中，本发明涉及一种在半导体结构中减少具有第一反射率的金属层的表观反射率的方法，包括在金属层上形成氮氧化硅抗反射涂层; 其中形成在所述金属层上的所述氧氮化硅抗反射涂层具有第二反射率，并且通过化学气相沉积在所述金属层上沉积氧氮化硅并在所述氧氮化物上形成氧化物层，并且所述第一反射率和所述第二反射率之间的差异至少约60％。

83. 发明授权

US06262484B1 Dual damascene method for backened metallization using poly stop layers 有权
公开(公告)号：US06262484B1
公开(公告)日：2001-07-17
申请号：US09295812
申请日：1999-04-20
申请人： Bharath Rangarajan , Ramkumar Subramanian , Bhanwar Singh
发明人： Bharath Rangarajan , Ramkumar Subramanian , Bhanwar Singh
IPC分类号： H01L23485
CPC分类号： H01L21/76807
摘要： A dual damascene process and structure for fabricating semiconductor devices are disclosed. In one embodiment of the invention, a protection layer is deposited on top of a metal layer to protect the metal layer during subsequent etching of an oxide layer to form the via and damascene trench. Because the selectivity between the oxide layer and the protection layer is high, the number and complexity of processing steps are thereby reduced. Other embodiments of the present invention use a metal sealant layer and/or anti-reflective coating in conjunction with the protection layer in a dual-damascene process.

84. 发明授权

US06982043B1 Scatterometry with grating to observe resist removal rate during etch 有权
标题翻译：用光栅进行散射测量以观察蚀刻期间的抗蚀剂去除率
公开(公告)号：US06982043B1
公开(公告)日：2006-01-03
申请号：US10382181
申请日：2003-03-05
申请人： Ramkumar Subramanian , Bharath Rangarajan , Catherine B. Labelle , Bhanwar Singh , Christopher F. Lyons
发明人： Ramkumar Subramanian , Bharath Rangarajan , Catherine B. Labelle , Bhanwar Singh , Christopher F. Lyons
IPC分类号： B44C1/22
CPC分类号： H01L22/12 , H01L22/26
摘要： Disclosed are a system and method for monitoring a patterned photoresist clad-wafer structure undergoing an etch process. The system includes a semiconductor wafer structure comprising a substrate, one or more intermediate layers overlying the substrate, and a first patterned photoresist layer overlying the intermediate layers, the semiconductor wafer structure being etched through one or more openings in the photoresist layer; a wafer-etch photoresist monitoring system programmed to obtain data relating to the photoresist layer as the etch process progresses; a pattern-specific grating aligned with the wafer structure and employed in conjunction with the monitoring system, the grating having at least one of a pitch and a critical dimension identical to the first patterned photoresist layer; and a wafer processing controller operatively connected to the monitoring system and adapted to receive data from the monitoring system in order to determine adjustments to a subsequent wafer clean process.
摘要翻译：公开了用于监测经历蚀刻工艺的图案化光致抗蚀剂包覆晶片结构的系统和方法。该系统包括半导体晶片结构，其包括衬底，覆盖衬底的一个或多个中间层和覆盖中间层的第一图案化光致抗蚀剂层，半导体晶片结构通过光致抗蚀剂层中的一个或多个开口进行蚀刻; 晶片蚀刻光刻胶监测系统被编程为随着蚀刻工艺的进行获得与光致抗蚀剂层有关的数据; 与晶片结构对准并与监视系统结合使用的图案特定光栅，光栅具有与第一图案化光致抗蚀剂层相同的间距和临界尺寸中的至少一个; 以及晶片处理控制器，可操作地连接到所述监控系统并且适于从所述监控系统接收数据，以便确定随后的晶片清洁过程的调整。

85. 发明授权

US06905950B2 Growing copper vias or lines within a patterned resist using a copper seed layer 有权
标题翻译：使用铜种子层在图案化抗蚀剂中生长铜通孔或线
公开(公告)号：US06905950B2
公开(公告)日：2005-06-14
申请号：US09893198
申请日：2001-06-27
申请人： Ramkumar Subramanian , Michael K. Templeton , Bhanwar Singh , Bharath Rangarajan
发明人： Ramkumar Subramanian , Michael K. Templeton , Bhanwar Singh , Bharath Rangarajan
IPC分类号： H01L21/768 , H01L21/3205
CPC分类号： H01L21/76885 , H01L21/76879
摘要： The present invention involves a method for fabricating interconnecting lines and vias. According to the invention, copper is grown within the openings in a patterned coating. The patterned coating can be a resist coating or a dielectric coating. Either type of coating can be formed over a copper seed layer, whereby the seed layer is exposed within the pattern gaps. The copper seed layer can also be provided within the pattern gaps after patterning. Copper features are grown within the pattern gaps by plating. Where the patterned coating is a resist, the resist is stripped leaving the copper features in the inverse pattern image. The copper features can be coated with a diffusion barrier layer and a dielectric. The dielectric is polished to leave the dielectric filling the spaces between copper features. The invention provides copper lines and vias without the need for a dielectric or metal etching step. Another benefit of the invention is that lines widths can be increased by trimming the patterned coating prior to growing the copper features.
摘要翻译：本发明涉及制造互连线和通孔的方法。根据本发明，铜在图案化涂层的开口内生长。图案化的涂层可以是抗蚀剂涂层或介电涂层。任何一种类型的涂层可以在铜籽晶层上形成，从而种子层在图案间隙内露出。图案化之后也可以在图案间隙内提供铜籽晶层。铜特征通过电镀在图案间隙内生长。在图案涂层是抗蚀剂的情况下，剥离抗蚀剂，留下逆向图案图案中的铜特征。铜的特征可以涂覆有扩散阻挡层和电介质。电介质被抛光以留下电介质填充铜特征之间的空间。本发明提供铜线和通孔，而不需要电介质或金属蚀刻步骤。本发明的另一个好处是通过在生长铜特征之前修整图案化涂层可以增加线宽。

86. 发明授权

US06879051B1 Systems and methods to determine seed layer thickness of trench sidewalls 失效
标题翻译：确定沟槽侧壁种子层厚度的系统和方法
公开(公告)号：US06879051B1
公开(公告)日：2005-04-12
申请号：US10050454
申请日：2002-01-16
申请人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Ramkumar Subramanian
发明人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Ramkumar Subramanian
IPC分类号： C23C16/04 , C23C16/52 , H01L21/31
CPC分类号： C23C16/045 , C23C16/52
摘要： One aspect of the present invention relates to a method to facilitate formation of seed layer portions on sidewall surfaces of a trench formed in a substrate. The method involves the steps of forming a conformal seed layer over a barrier layer disposed conformal to a trench, wherein the trench is formed in the substrate; reflecting a light beam of x-ray radiation at the seed layer sidewall portions; generating a measurement signal based on the reflected portion of the light beam; and determining a thickness of the sidewall portions based on the measurement signal while the sidewall portions are being formed over the trench.
摘要翻译：本发明的一个方面涉及一种促进在衬底中形成的沟槽的侧壁表面上形成种子层部分的方法。该方法包括以下步骤：在与沟槽共形设置的阻挡层上形成保形种子层，其中沟槽形成在衬底中; 在种子层侧壁部分反射x射线辐射的光束; 基于所述光束的反射部分生成测量信号; 以及当在所述沟槽上形成所述侧壁部分时，基于所述测量信号来确定所述侧壁部分的厚度。

87. 发明授权

US06704101B1 Scatterometry based measurements of a moving substrate 失效
标题翻译：移动基板的基于散射法的测量
公开(公告)号：US06704101B1
公开(公告)日：2004-03-09
申请号：US10050423
申请日：2002-01-16
申请人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian , Michael K. Templeton
发明人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian , Michael K. Templeton
IPC分类号： G01N2100
CPC分类号： G01N21/47 , G01N21/4788 , G01N21/55 , G01N21/9501 , G01N2201/10
摘要： A system and method are disclosed for monitoring characteristics of a substrate. A substrate is supported for movement within a processing environment and an incident light beam is emitted onto a surface of the substrate. The incident beam is provided to a moveable reflector that directs the beam to the substrate. A control system controls movement of the reflector so as to selectively interrogates the substrate with the beam.
摘要翻译：公开了用于监测基板的特性的系统和方法。支撑衬底在处理环境中移动，并且将入射光束发射到衬底的表面上。入射光束被提供到将光束引导到衬底的可移动反射器。控制系统控制反射器的运动，以便选择性地用光束询问衬底。

88. 发明授权

US06650422B2 Scatterometry techniques to ascertain asymmetry profile of features and generate a feedback or feedforward process control data associated therewith 有权
标题翻译：散射技术来确定特征的不对称轮廓，并产生与之相关联的反馈或前馈过程控制数据
公开(公告)号：US06650422B2
公开(公告)日：2003-11-18
申请号：US09817820
申请日：2001-03-26
申请人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Ramkumar Subramanian
发明人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Ramkumar Subramanian
IPC分类号： G01B1100
CPC分类号： G01B11/30 , G01B11/24 , G01B11/26 , G01N21/211 , G01N21/4738 , G01N21/9501
摘要： The present invention is directed to a method and a system for non-destructively, efficiently and accurately detecting asymmetry in the profile of a feature formed on a wafer during the process of semiconductor fabrication. The method encompasses directing a beam of light or radiation at a feature and detecting a reflected beam associated therewith. Data associated with the reflected beam is correlated with data associated with known feature profiles to ascertain profile characteristics associated with the feature of interest. Using the profile characteristics, an asymmetry of the feature is determined which is then used to generate feedback or feedforward process control data to compensate for or correct such asymmetry in subsequent processing.
摘要翻译：本发明涉及一种用于在半导体制造过程中非破坏性地，有效地和准确地检测在晶片上形成的特征的轮廓的不对称性的方法和系统。该方法包括在特征处引导光束或辐射，并且检测与其相关联的反射光束。与反射光束相关联的数据与与已知特征轮廓相关联的数据相关联，以确定与感兴趣特征相关联的轮廓特征。使用简档特征，确定特征的不对称性，然后将其用于产生反馈或前馈过程控制数据，以补偿或纠正随后处理中的这种不对称性。

89. 发明授权

US06579733B1 Using scatterometry to measure resist thickness and control implant 有权
公开(公告)号：US06579733B1
公开(公告)日：2003-06-17
申请号：US10196407
申请日：2002-07-16
申请人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
发明人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： H01L2166
CPC分类号： H01L22/12
摘要： The present invention provides systems and methods wherein scatterometry is used to control an implant processes, such as an angled implant process. According to the invention, data relating to resist dimensions is obtained by scatterometry prior to an the implant process. The data is used to determine whether a resist is suitable for an implant process and/or determine an appropriate condition, such as an angle of implant or implantation dose, for an implant process.

90. 发明授权

US06561706B2 Critical dimension monitoring from latent image 有权
公开(公告)号：US06561706B2
公开(公告)日：2003-05-13
申请号：US09893807
申请日：2001-06-28
申请人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Ramkumar Subramanian
发明人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Ramkumar Subramanian
IPC分类号： G03D500
CPC分类号： G03F7/70633 , G03F7/70675
摘要： A system for monitoring a latent image exposed in a photo resist during semiconductor manufacture is provided. The system includes one or more light sources, each light source directing light to the latent image and/or one or more gratings exposed on one or more portions of a wafer. Light reflected from the latent image and/or the gratings is collected by a signature system, which processes the collected light. Light passing through the latent image and/or gratings may similarly be collected by the signature system, which processes the collected light. The collected light is analyzed and can be employed to generate feedback information to control the exposure. The collect light is further analyzed and can be employed to generate feed forward information that can be employed to control post exposure processes including development and baking processes.

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