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81. 发明申请

US20090020819A1 FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：具有合并源/排水硅酸盐的FIN型场效应晶体管结构及形成结构的方法
公开(公告)号：US20090020819A1
公开(公告)日：2009-01-22
申请号：US11778217
申请日：2007-07-16
申请人： Brent A. Anderson , Andres Bryant , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.
摘要翻译：这里公开了多鳍片式场效应晶体管（即，多鳍式双栅极或三栅极场效应晶体管）的实施例，其中多个散热片部分或完全由高导电材料（例如，金属硅化物）。以这种方式合并散热片使串联电阻最小化，栅极和源极/漏极区之间的寄生电容几乎不增加。以这种方式合并半导体散热片也允许每个源极/漏极区域通过单个触点通孔接触，以及该触点通孔的更灵活的放置。

82. 发明授权

US07473605B2 Corner dominated trigate field effect transistor 有权
标题翻译：角主导的立体场效应晶体管
公开(公告)号：US07473605B2
公开(公告)日：2009-01-06
申请号：US11866435
申请日：2007-10-03
申请人： Brent A. Anderson , Andres Bryant , Jeffrey B. Johnson , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Jeffrey B. Johnson , Edward J. Nowak
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： Disclosed are embodiments of a trigate field effect transistor that comprises a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. Thick gate dielectric layers separate the top surface and opposing sidewalls of the channel region from the gate conductor in order to suppress conductivity in the channel planes. A thin gate dielectric layer separates the upper corners of the channel region from the gate conductor in order to optimize conductivity in the channel corners. To further emphasize the current flow in the channel corners, the source/drain regions can be formed in the upper corners of the semiconductor body alone. Alternatively, source/drain extension regions can be formed only in the upper corners of the semiconductor body adjacent to the gate conductor and deep source/drain diffusion regions can be formed in the ends of the semiconductor body.
摘要翻译：公开了一种触发场效应晶体管的实施例，其包括具有沟道区的鳍状半导体本体和沟道区两侧的源极/漏极区。厚栅电介质层将沟道区的顶表面和相对的侧壁与栅极导体分开，以便抑制沟道平面中的导电性。薄栅极电介质层将沟道区的上角与栅极导体分开，以便优化沟道角中的导电性。为了进一步强调通道角中的电流流动，源极/漏极区域可以单独形成在半导体主体的上角部。或者，源极/漏极延伸区域仅可以形成在与栅极导体相邻的半导体本体的上角处，并且可以在半导体本体的端部形成深的源极/漏极扩散区域。

83. 发明申请

US20080185644A1 FETS WITH SELF-ALIGNED BODIES AND BACKGATE HOLES 有权
标题翻译：具有自对准体和背部孔的FET
公开(公告)号：US20080185644A1
公开(公告)日：2008-08-07
申请号：US11539288
申请日：2006-10-06
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Richard Q. Williams
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78612 , H01L29/66772 , H01L29/78621 , H01L29/78648
摘要： A FET has a shallow source/drain region, a deep channel region, a gate stack and a back gate that is surrounded by dielectric. The FET structure also includes halo or pocket implants that extend through the entire depth of the channel region. Because a portion of the halo and well doping of the channel is deeper than the source/drain depth, better threshold voltage and process control is achieved. A back-gated FET structure is also provided having a first dielectric layer in this structure that runs under the shallow source/drain region between the channel region and the back gate. This first dielectric layer extends from under the source/drain regions on either side of the back gate and is in contact with a second dielectric such that the back gate is bounded on each side or isolated by dielectric.
摘要翻译： FET具有浅电源/漏极区域，深沟道区域，栅极堆叠和被电介质包围的背栅极。 FET结构还包括延伸通过通道区域的整个深度的晕或凹坑植入物。因为沟道的一部分光晕和阱掺杂比源极/漏极深度更深，所以实现了更好的阈值电压和过程控制。还提供了后栅化FET结构，其具有在该结构中的第一介电层，其在沟道区域和后栅极之间的浅源极/漏极区域下方延伸。该第一电介质层从背栅的两侧的源极/漏极区下方延伸并与第二电介质接触，使得后栅极在每一侧上界定或通过电介质隔离。

84. 发明申请

US20080116517A1 Dual stress device and method 有权
标题翻译：双重应力装置及方法
公开(公告)号：US20080116517A1
公开(公告)日：2008-05-22
申请号：US11561488
申请日：2006-11-20
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/78 , H01L29/786 , H01L21/84 , H01L21/336
CPC分类号： H01L29/785 , H01L21/31155 , H01L21/76283 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1203 , H01L29/1037 , H01L29/66621 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.
摘要翻译：一种包括半导体材料的半导体器件，该半导体材料具有形成在该弯曲处的弯曲部和沟槽特征，以及至少部分地设置在沟槽特征中的栅极结构。一种制造半导体结构的方法，包括在层上形成具有沟槽特征的半导体材料，在沟槽特征中至少部分地形成栅极结构，以及弯曲半导体材料，使得在反转沟道中的半导体材料中产生应力栅结构的区域。

85. 发明授权

US07335563B2 Rotated field effect transistors and method of manufacture 有权
标题翻译：旋转场效应晶体管及其制造方法
公开(公告)号：US07335563B2
公开(公告)日：2008-02-26
申请号：US11164070
申请日：2005-11-09
申请人： Brent A. Anderson , Andres Bryant , Myung-hee Na , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Myung-hee Na , Edward J. Nowak
IPC分类号： H01L21/336
CPC分类号： H01L29/78621 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/66772
摘要： An apparatus and method for manufacturing rotated field effect transistors. The method comprises providing a substrate including a first gate structure and a second gate structure, which are not parallel to each other. The method further includes performing a first ion implant substantially orthogonal to an edge of the first gate structure to form a first impurity region and performing a second ion implant at a direction different than that of the first ion implant and substantially orthogonal to an edge of the second gate structure to form a second impurity region under the edge of the second gate structure.
摘要翻译：用于制造旋转场效应晶体管的装置和方法。该方法包括提供包括彼此不平行的第一栅极结构和第二栅极结构的衬底。该方法还包括执行基本上与第一栅极结构的边缘正交的第一离子注入以形成第一杂质区域，并且在不同于第一离子注入的方向上执行第二离子注入并且基本上垂直于第第二栅极结构，以在第二栅极结构的边缘下方形成第二杂质区域。

86. 发明授权

US07274053B2 Fin device with capacitor integrated under gate electrode 有权
标题翻译：带电容器的Fin器件集成在栅电极下
公开(公告)号：US07274053B2
公开(公告)日：2007-09-25
申请号：US10904357
申请日：2004-11-05
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L27/148
CPC分类号： H01L29/785 , H01L27/1203 , H01L29/66795
摘要： A fin-type field effect transistor (FinFET) has a fin having a center channel portion, end portions comprising source and drain regions, and channel extensions extending from sidewalls of the channel portion of the fin. The structure also includes a gate insulator covering the channel portion and the channel extensions, and a gate conductor on the gate insulator. The channel extensions increase capacitance of the channel portion of the fin.
摘要翻译：翅片型场效应晶体管（FinFET）具有鳍状物，其具有中心沟道部分，端部包括源极和漏极区域以及从鳍片的沟道部分的侧壁延伸的沟道延伸部。该结构还包括覆盖沟道部分和沟道延伸部的栅极绝缘体以及栅极绝缘体上的栅极导体。通道扩展增加了鳍片的通道部分的电容。

87. 发明授权

US07105934B2 FinFET with low gate capacitance and low extrinsic resistance 有权
标题翻译： FinFET具有低栅极电容和低外部电阻
公开(公告)号：US07105934B2
公开(公告)日：2006-09-12
申请号：US10711170
申请日：2004-08-30
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/76 , H01L21/332 , H01L21/335
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795 , Y10S257/90
摘要： A FinFET device and a method of lowering a gate capacitance and extrinsic resistance in a field effect transistor, wherein the method comprises forming an isolation layer comprising a BOX layer over a substrate, configuring source/drain regions above the isolation layer, forming a fin structure over the isolation layer, configuring a first gate electrode adjacent to the fin structure, disposing a gate insulator between the first gate electrode and the fin structure, positioning a second gate electrode transverse to the first gate electrode, and depositing a third gate electrode on the fin structure, the first gate electrode, and the second gate electrode, wherein the isolation layer is formed beneath the insulator, the first gate electrode, and the fin structure. The method further comprises sandwiching the second gate electrode with a dielectric material. The fin structure is formed by depositing an oxide layer over a silicon layer.
摘要翻译： FinFET器件和降低场效应晶体管中的栅极电容和外在电阻的方法，其中所述方法包括在衬底上形成包括BOX层的隔离层，在隔离层上方构成源/漏区，形成鳍结构在所述隔离层上方配置与所述鳍结构相邻的第一栅电极，在所述第一栅电极和所述鳍结构之间设置栅极绝缘体，将第二栅电极定位成横向于所述第一栅电极，以及将第三栅电极鳍结构，第一栅电极和第二栅电极，其中隔离层形成在绝缘体下方，第一栅电极和鳍结构之下。该方法还包括用电介质材料夹住第二栅电极。翅片结构通过在硅层上沉积氧化物层而形成。

88. 发明授权

US06947275B1 Fin capacitor 失效
标题翻译：散热片电容
公开(公告)号：US06947275B1
公开(公告)日：2005-09-20
申请号：US10711975
申请日：2004-10-18
申请人： Brent A Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
发明人： Brent A Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01G4/005 , H01G4/012 , H01G4/06 , H01G4/33 , H01L21/02 , H01L21/8242 , H01L21/84 , H01L27/108 , H01L27/13
CPC分类号： H01G4/012 , H01G4/06 , H01G4/33 , H01L21/84 , H01L27/1085 , H01L27/13 , H01L28/92 , Y10T29/435
摘要： Disclosed is a capacitor structure and method for forming the same. This structure has a conductive substrate, conductive fins extending above the substrate, and trenches extending into the substrate. These trenches are positioned between locations where the fins extend above the substrate. The invention includes an insulator in the trenches and covering the fins. This insulator separates the substrate and fins from a conductive top plate that covers the fins and fills the trenches. A bottom plate contact electrically connects the fins and the substrate such that the fins and the substrate comprise a bottom plate of the capacitor structure.
摘要翻译：公开了一种电容器结构及其形成方法。该结构具有导电基板，在基板上方延伸的导电翅片和延伸到基板中的沟槽。这些沟槽位于翅片在衬底上方延伸的位置之间。本发明包括沟槽中的绝缘体并覆盖翅片。该绝缘体将基板和散热片与覆盖翅片的导电顶板隔开并填充沟槽。底板接触件电连接散热片和基板，使得散热片和基板包括电容器结构的底板。

89. 发明授权

US06774437B2 Fin-based double poly dynamic threshold CMOS FET with spacer gate and method of fabrication 有权
标题翻译：基于鳍的双重多晶硅动态阈值CMOS FET与间隔栅极和制造方法
公开(公告)号：US06774437B2
公开(公告)日：2004-08-10
申请号：US09683486
申请日：2002-01-07
申请人： Andres Bryant , K. Paul Muller , Edward J. Nowak
发明人： Andres Bryant , K. Paul Muller , Edward J. Nowak
IPC分类号： H01L2704
CPC分类号： H01L29/785 , H01L21/2815 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795 , H01L29/783
摘要： The present invention provides a dynamic threshold (DT) CMOS FET and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a DT CMOS FET with a short, low resistance connection between the gate and the body and with low body-to-source/drain capacitance. The low body-to-source/drain capacitance is achieved using a thin, fin-type body. The low resistance connection between the gate and the body contact is achieved by having the gate and body contact aligned on opposite long sides of the fin with a bridge over the top of the narrow fin electrically connecting the gate and body.
摘要翻译：本发明提供一种动态阈值（DT）CMOS FET及其形成方法，其导致改进的器件性能和密度。本发明的优选实施例提供了一种DT CMOS FET，其在栅极和主体之间具有短的低电阻连接，并且具有低的体/源极/漏极电容。使用薄的鳍式体实现了较低的体源对漏极电容。栅极和体接触之间的低电阻连接是通过使栅极和主体接触在翅片的相对的长边上对准来实现的，桥与电极连接门和主体的窄鳍的顶部之间形成桥。

90. 发明授权

US06552396B1 Matched transistors and methods for forming the same 失效
标题翻译：匹配的晶体管及其形成方法
公开(公告)号：US06552396B1
公开(公告)日：2003-04-22
申请号：US09524295
申请日：2000-03-14
申请人： Andres Bryant , William F. Clark, Jr. , Edward J. Nowak , Minh H. Tong
发明人： Andres Bryant , William F. Clark, Jr. , Edward J. Nowak , Minh H. Tong
IPC分类号： H01L2701
CPC分类号： H01L27/1203 , H01L21/84
摘要： An SOI multiple FET structure is provided that comprises a substrate having a substrate layer on an insulator layer. The SOI multiple FET structure includes distal diffusion regions in the substrate layer and a central diffusion region in the substrate layer. The central diffusion region has a width and extends from a surface of the substrate layer downward into contact with the insulator layer along a portion of the width and extends only partially into the substrate layer along another portion of the width. The SOI multiple FET structure also includes a pair of gates on the surface of the substrate layer each overlapping one of the distal diffusion regions and the central diffusion region; and a pair of body regions in the substrate layer each under one of the gates for forming a channel between the one of the distal diffusion regions and the central diffusion region. The body regions are in electrical communication under the another portion of the width of the central diffusion region. Methods for forming the SOI multiple FET structure are also provided.
摘要翻译：提供了SOI多FET结构，其包括在绝缘体层上具有衬底层的衬底。 SOI多FET结构包括衬底层中的远端扩散区域和衬底层中的中心扩散区域。中心扩散区具有宽度并且从衬底层的表面向下延伸，沿着宽度的一部分与绝缘体层接触，并且沿宽度的另一部分仅部分地延伸到衬底层中。 SOI多FET结构还包括在衬底层的表面上的一对栅极，每个栅极重叠远端扩散区域和中心扩散区域之一; 以及在所述基板层中的一个所述栅极之间的一对体区，用于在所述远侧扩散区域和所述中央扩散区域中的一个之间形成沟道。身体区域在中央扩散区域的宽度的另一部分下电连通。还提供了形成SOI多FET结构的方法。

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