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81. 发明授权

US08654602B2 Pseudo-inverter circuit on SeOI 有权
标题翻译： SeOI上的伪逆变电路
公开(公告)号：US08654602B2
公开(公告)日：2014-02-18
申请号：US13495632
申请日：2012-06-13
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C11/4085 , G11C2211/4016
摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
摘要翻译：在绝缘体上半导体衬底上制成的电路。该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

82. 发明申请

US20110242926A1 PSEUDO-INVERTER CIRCUIT ON SeO1 有权
标题翻译： PSO1上的PSEUDO-INVERTER电路
公开(公告)号：US20110242926A1
公开(公告)日：2011-10-06
申请号：US12793553
申请日：2010-06-03
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： G11C8/08 , G05F1/10
CPC分类号： G11C8/08 , G11C11/4085 , G11C2211/4016
摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
摘要翻译：在绝缘体上半导体衬底上制成的电路。该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

83. 发明授权

US07943988B2 Power MOSFET with a gate structure of different material 有权
标题翻译：功率MOSFET具有栅极结构不同的材料
公开(公告)号：US07943988B2
公开(公告)日：2011-05-17
申请号：US12205438
申请日：2008-09-05
申请人： Daniel Pham , Bich-Yen Nguyen
发明人： Daniel Pham , Bich-Yen Nguyen
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L21/28105 , H01L29/42372
摘要： A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.
摘要翻译：半导体器件包括第一导电类型和第一掺杂浓度的半导体层。用作第一导电类型的漏极的第一半导体区域具有比半导体层更低的掺杂浓度，并且在半导体层之上。栅极电介质在第一半导体区域之上。栅极电介质上的栅极电极在中心部分的相对侧上具有含金属的中心部分和第一和第二硅部分。用作第二导电类型的沟道的第二半导体区域具有在第一硅部分下面的第一部分和栅极电介质。用作第一导电类型的源的第三半导体区域与第二半导体区域的第一部分横向相邻。置换硅的含金属中心部分将源极增加到漏极击穿电压。

84. 发明授权

US07800141B2 Electronic device including a semiconductor fin 有权
标题翻译：包括半导体鳍片的电子设备
公开(公告)号：US07800141B2
公开(公告)日：2010-09-21
申请号：US12174357
申请日：2008-07-16
申请人： Da Zhang , Bich-Yen Nguyen
发明人： Da Zhang , Bich-Yen Nguyen
IPC分类号： H01L29/06
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66507 , H01L29/66795 , H01L29/78684
摘要： An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.
摘要翻译：电子器件可以包括覆盖绝缘层的半导体鳍片。电子器件还可以包括覆盖半导体鳍片的半导体层。半导体层可以具有彼此间隔开的第一部分和第二部分。在一个方面，电子设备可以包括位于半导体层的第一和第二部分之间并与之隔开的导电构件。电子器件还可以包括覆盖半导体层的金属 - 半导体层。在另一方面，半导体层可以邻接半导体鳍并包括掺杂剂。在另一方面，形成电子器件的方法可以包括使含金属层和半导体层反应以形成金属 - 半导体层。在另一方面，一种方法可以包括形成邻接半导体鳍片的壁表面的包括掺杂剂的半导体层。

85. 发明申请

US20090146180A1 LDMOS WITH CHANNEL STRESS 有权
标题翻译： LDMOS与通道应力
公开(公告)号：US20090146180A1
公开(公告)日：2009-06-11
申请号：US11951702
申请日：2007-12-06
申请人： Xiaoqiu Huang , Veeraraghavan Dhandapani , Bich-Yen Nguyen , Amanda M. Kroll , Daniel T. Pham
发明人： Xiaoqiu Huang , Veeraraghavan Dhandapani , Bich-Yen Nguyen , Amanda M. Kroll , Daniel T. Pham
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66659 , H01L29/7781
摘要： A method of forming a metal oxide semiconductor (MOS) device comprises defining an active area in an unstrained semiconductor layer structure, depositing a hard mask overlying the active area and a region outside of the active area, patterning the hard mask to expose the active area, selectively growing a strained semiconductor layer overlying the exposed active area, and forming a remainder of the MOS device. The active area includes a first doped region of first conductivity type and a second doped region of second conductivity type. The strained semiconductor layer provides a biaxially strained channel for the MOS device. During a portion of forming the remainder of the MOS device, dopant of the first conductivity type of the first doped region of the active area and dopant of the second conductivity type of the second doped region of the active area diffuses into overlying portions of the strained semiconductor layer to create a correspondingly doped strained semiconductor layer, thereby providing corresponding doping for the biaxially strained channel.
摘要翻译：一种形成金属氧化物半导体（MOS）器件的方法包括：在非限制性半导体层结构中限定有源区，沉积覆盖有源区的硬掩模和有源区外的区域，使硬掩模图形化以暴露有源区选择性地生长覆盖暴露的有源区的应变半导体层，以及形成MOS器件的其余部分。有源区包括第一导电类型的第一掺杂区和第二导电类型的第二掺杂区。应变半导体层为MOS器件提供双向应变通道。在形成MOS器件的其余部分的部分期间，有源区的第一掺杂区的第一导电类型的掺杂剂和有源区的第二掺杂区的第二导电类型的掺杂剂扩散到应变的上覆部分以产生相应掺杂的应变半导体层，从而为双轴应变通道提供相应的掺杂。

86. 发明授权

US07446026B2 Method of forming a CMOS device with stressor source/drain regions 有权
标题翻译：形成具有应力源/漏极区域的CMOS器件的方法
公开(公告)号：US07446026B2
公开(公告)日：2008-11-04
申请号：US11349595
申请日：2006-02-08
申请人： Da Zhang , Bich-Yen Nguyen
发明人： Da Zhang , Bich-Yen Nguyen
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/8238 , H01L21/8234
CPC分类号： H01L21/823842 , H01L21/823814 , H01L29/7848
摘要： A method for forming a semiconductor device includes providing a semiconductor substrate having a first doped region and a second doped region, providing a dielectric over the first doped region and the second doped region, and forming a first gate stack over the dielectric over at least a portion of the first doped region. The first gate stack includes a metal portion over the dielectric, a first in situ doped semiconductor portion over the metal portion, and a first blocking cap over the in situ doped semiconductor portion. The method further includes performing implantations to form source/drain regions adjacent the first and second gate stack, where the first blocking cap has a thickness sufficient to substantially block implant dopants from entering the first in situ doped semiconductor portion. Source/drain embedded stressors are also formed.
摘要翻译：一种用于形成半导体器件的方法包括提供具有第一掺杂区域和第二掺杂区域的半导体衬底，在第一掺杂区域和第二掺杂区域上提供电介质，以及在电介质上至少形成第一栅极叠层第一掺杂区域的一部分。第一栅极堆叠包括电介质上的金属部分，金属部分上方的第一原位掺杂半导体部分以及原位掺杂半导体部分上的第一阻挡盖。该方法还包括执行注入以形成与第一和第二栅极堆叠相邻的源极/漏极区域，其中第一阻挡盖具有足以基本上阻挡注入掺杂剂进入第一原位掺杂半导体部分的厚度。源/漏嵌入式应力源也形成。

87. 发明授权

US07413970B2 Process of forming an electronic device including a semiconductor fin 有权
标题翻译：形成包括半导体鳍片的电子器件的工艺
公开(公告)号：US07413970B2
公开(公告)日：2008-08-19
申请号：US11375894
申请日：2006-03-15
申请人： Da Zhang , Bich-Yen Nguyen
发明人： Da Zhang , Bich-Yen Nguyen
IPC分类号： H01L29/06 , H01L21/3205
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66507 , H01L29/66795 , H01L29/78684
摘要： An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.
摘要翻译：电子器件可以包括覆盖绝缘层的半导体鳍片。电子器件还可以包括覆盖半导体鳍片的半导体层。半导体层可以具有彼此间隔开的第一部分和第二部分。在一个方面，电子设备可以包括位于半导体层的第一和第二部分之间并与之隔开的导电构件。电子器件还可以包括覆盖半导体层的金属 - 半导体层。在另一方面，半导体层可以邻接半导体鳍并包括掺杂剂。在另一方面，形成电子器件的方法可以包括使含金属层和半导体层反应以形成金属 - 半导体层。在另一方面，一种方法可以包括形成邻接半导体鳍片的壁表面的包括掺杂剂的半导体层。

88. 发明申请

US20070238250A1 Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor 失效
标题翻译：使用蚀刻停止层的半导体制造工艺来优化源极/漏极应力源的形成
公开(公告)号：US20070238250A1
公开(公告)日：2007-10-11
申请号：US11393340
申请日：2006-03-30
申请人： Da Zhang , Ted White , Bich-Yen Nguyen
发明人： Da Zhang , Ted White , Bich-Yen Nguyen
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/76254 , H01L21/76283 , H01L29/66772 , H01L29/78684
摘要： A semiconductor fabrication process includes forming an etch stop layer (ESL) overlying a buried oxide (BOX) layer and an active semiconductor layer overlying the ESL. A gate electrode is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors are formed on the ESL where the source/drain stressors strain the transistor channel. Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75° C. may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium. The source/drain stressors may be silicon germanium having a second percentage of germanium for P-type transistors, and they may be silicon carbon for N-type transistors.
摘要翻译：半导体制造工艺包括形成覆盖掩埋氧化物（BOX）层和覆盖ESL的有源半导体层的蚀刻停止层（ESL）。形成覆盖有源半导体层的栅电极。蚀刻有源半导体层的源极/漏极区域以露出ESL。源极/漏极应力源在ESL上形成，其源极/漏极应力应变应变晶体管沟道。形成ESL可以包括外延生长厚度为约30nm或更小的硅锗ESL。优选地，有源半导体层蚀刻速率与ESL蚀刻速率的比率超过10:1。使用加热到约75℃温度的NH 4 OH：H 2 O 2的溶液进行湿蚀刻可以用于蚀刻源/漏区。 ESL可以是具有第一百分比的锗的硅锗。源极/漏极应力源可以是对于P型晶体管具有第二百分比的锗的硅锗，并且它们可以是N型晶体管的硅碳。

89. 发明申请

US20070238233A1 Method of making a multiple crystal orientation semiconductor device 有权
标题翻译：制造多晶体取向半导体器件的方法
公开(公告)号：US20070238233A1
公开(公告)日：2007-10-11
申请号：US11393563
申请日：2006-03-30
申请人： Mariam Sadaka , Bich-Yen Nguyen , Ted White
发明人： Mariam Sadaka , Bich-Yen Nguyen , Ted White
IPC分类号： H01L21/337
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L27/1207
摘要： A method of having transistors formed in enhanced performance crystal orientations begins with a wafer having a semiconductor substrate (12,52) of a first surface orientation, a thin etch stop layer (14,54) on the semiconductor substrate, a buried oxide layer (16,56) on the thin etch stop layer, and a semiconductor layer (18,58) of a second surface orientation on the buried oxide layer. An etch penetrates to the thin etch stop layer. Another etch, which is chosen to minimize the damage to the underlying semiconductor substrate, exposes a portion of the semiconductor substrate. An epitaxial semiconductor (28,66) is then grown from the exposed portion of the semiconductor substrate to form a semiconductor region having the first surface orientation and having few, if any, defects. The epitaxially grown semiconductor region is then used for enhancing one type of transistor while the semiconductor layer of the second surface orientation is used for enhancing a different type of transistor.
摘要翻译：以增强的性能晶体取向形成的晶体管的方法从具有第一表面取向的半导体衬底（12,52），半导体衬底上的薄蚀刻停止层（14,54），掩埋氧化物层（ 16,56）和在所述掩埋氧化物层上的第二表面取向的半导体层（18,58）。蚀刻渗透到薄的蚀刻停止层。被选择以最小化对下面的半导体衬底的损害的另一蚀刻暴露了半导体衬底的一部分。然后从半导体衬底的暴露部分生长外延半导体（28,66）以形成具有第一表面取向并且具有很少（如果有的话）缺陷的半导体区域。然后外延生长的半导体区域用于增强一种类型的晶体管，而第二表面取向的半导体层用于增强不同类型的晶体管。

90. 发明申请

US20070215908A1 Electronic device including a semiconductor fin and a process for forming the electronic device 有权
标题翻译：包括半导体鳍片的电子设备和用于形成电子设备的工艺
公开(公告)号：US20070215908A1
公开(公告)日：2007-09-20
申请号：US11375894
申请日：2006-03-15
申请人： Da Zhang , Bich-Yen Nguyen
发明人： Da Zhang , Bich-Yen Nguyen
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66507 , H01L29/66795 , H01L29/78684
摘要： An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.
摘要翻译：电子器件可以包括覆盖绝缘层的半导体鳍片。电子器件还可以包括覆盖半导体鳍片的半导体层。半导体层可以具有彼此间隔开的第一部分和第二部分。在一个方面，电子设备可以包括位于半导体层的第一和第二部分之间并与之隔开的导电构件。电子器件还可以包括覆盖半导体层的金属 - 半导体层。在另一方面，半导体层可以邻接半导体鳍并包括掺杂剂。在另一方面，形成电子器件的方法可以包括使含金属层和半导体层反应以形成金属 - 半导体层。在另一方面，一种方法可以包括形成邻接半导体鳍片的壁表面的包括掺杂剂的半导体层。

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