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81. 发明申请

US20130173515A1 ELECTRONIC SYNAPSES FROM STOCHASTIC BINARY MEMORY DEVICES 有权
标题翻译：来自STCCHASTIC二进制存储器件的电子快照
公开(公告)号：US20130173515A1
公开(公告)日：2013-07-04
申请号：US13611722
申请日：2012-09-12
申请人： Bipin Rajendran , Mark B. Ritter
发明人： Bipin Rajendran , Mark B. Ritter
IPC分类号： G06N3/04
CPC分类号： G06N3/0635 , G06N3/04 , G06N3/049
摘要： According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.
摘要翻译：根据技术，电子设备被配置为对应于生物突触的特征。电子装置包括平行布置的多个双极性电阻器以形成电子突触，连接到电子突触的一端和第一电子神经元的轴突连接，以及连接到电子突触的另一端的树突状连接和第二电子神经元。电子突触中突触传导的增加和减少是基于在低电阻状态和高电阻状态之间切换多个双极性电阻器的概率。

82. 发明授权

US08350316B2 Phase change memory cells having vertical channel access transistor and memory plane 有权
标题翻译：具有垂直通道存取晶体管和存储器平面的相变存储单元
公开(公告)号：US08350316B2
公开(公告)日：2013-01-08
申请号：US12471287
申请日：2009-05-22
申请人： Hsiang-Lan Lung , Chung Hon Lam , Ming-Hsiu Lee , Bipin Rajendran
发明人： Hsiang-Lan Lung , Chung Hon Lam , Ming-Hsiu Lee , Bipin Rajendran
IPC分类号： H01L29/732
CPC分类号： H01L27/101 , G11C13/0004 , H01L27/2454 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.
摘要翻译：描述存储器件以及制造方法。如本文所述的存储器件包括覆盖多个位线的多个字线和多个场效应晶体管。多个场效应晶体管中的场效应晶体管包括电耦合到多个位线中的相应位线的第一端子，覆盖第一端子的第二端子和分离第一和第二端子并且相邻多行字线中的字线。相应的字线用作场效应晶体管的栅极。电介质将对应的字线与沟道区分开。存储器平面包括电耦合到场效应晶体管的相应第二端子的可编程电阻存储器材料，以及可编程电阻存储器材料上的导体材料并耦合到公共电压。

83. 发明授权

US08030634B2 Memory array with diode driver and method for fabricating the same 有权
标题翻译：具有二极管驱动器的存储器阵列及其制造方法
公开(公告)号：US08030634B2
公开(公告)日：2011-10-04
申请号：US12060075
申请日：2008-03-31
申请人： Hsiang-Lan Lung , Min Yang , Thomas D. Happ , Bipin Rajendran
发明人： Hsiang-Lan Lung , Min Yang , Thomas D. Happ , Bipin Rajendran
IPC分类号： H01L29/02 , H01L47/00
CPC分类号： H01L27/24
摘要： A memory array with self-centered diode access devices results from a process in which diodes are formed in the fill material, each diode having a lightly-doped first layer of the same conductivity type as the conductive lines; a heavily doped second layer of opposite conductivity type; and a conductive cap. Self-aligned, and self-centered spacers in the self-aligned vias define pores that expose the conductive cap. Memory material is deposited within the pores, the memory material making contact with the conductive cap. A top electrode is formed in contact with the memory material.
摘要翻译：具有自中心二极管接入装置的存储器阵列是由填充材料中形成二极管的过程产生的，每个二极管具有与导电线相同导电类型的轻掺杂第一层; 相反导电类型的重掺杂第二层; 和导电帽。自对准和自对准的自对准通孔中的间隔物限定暴露导电盖的孔。记忆材料沉积在孔内，记忆材料与导电帽接触。形成与记忆材料接触的顶部电极。

84. 发明授权

US07863610B2 Integrated circuit including silicide region to inhibit parasitic currents 有权
标题翻译：集成电路包括硅化物区域以抑制寄生电流
公开(公告)号：US07863610B2
公开(公告)日：2011-01-04
申请号：US11843044
申请日：2007-08-22
申请人： Bipin Rajendran , Shoaib Hasan.Zaidi
发明人： Bipin Rajendran , Shoaib Hasan.Zaidi
IPC分类号： H01L29/10 , H01L21/70
CPC分类号： H01L27/1021 , G11C13/0004 , G11C2213/72 , H01L27/24
摘要： An integrated circuit is disclosed. One embodiment includes a first diode, a second diode, and a semiconductor line coupled to the first diode and the second diode. The line includes a first silicide region between the first diode and the second diode.
摘要翻译：公开了一种集成电路。一个实施例包括第一二极管，第二二极管和耦合到第一二极管和第二二极管的半导体线。该线包括在第一二极管和第二二极管之间的第一硅化物区域。

85. 发明授权

US07811879B2 Process for PCM integration with poly-emitter BJT as access device 有权
标题翻译：与多发射器BJT作为接入设备的PCM集成过程
公开(公告)号：US07811879B2
公开(公告)日：2010-10-12
申请号：US12121875
申请日：2008-05-16
申请人： Chung Hon Lam , Bipin Rajendran
发明人： Chung Hon Lam , Bipin Rajendran
IPC分类号： H01L21/8249
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/101
摘要： Techniques for forming a memory cell. An aspect of the invention includes forming FET gate stacks and sacrificial cell gate stacks over the substrate. Spacer layers are then formed around the FET gate stacks and around the sacrificial cell gate stacks. The sacrificial cell gate stacks are then removed such that the spacer layers around the sacrificial cell gate stacks are still intact. BJT cell stacks are then formed in the space between the spacer layers where the sacrificial cell gate stacks were formed and removed, the BJT cell stacks including an emitter layer. A phase change layer above the emitter contacts and an electrode above the phase change layer are then formed.
摘要翻译：形成记忆体的技术。本发明的一个方面包括在衬底上形成FET栅极叠层和牺牲电池栅叠层。然后在FET栅极堆叠周围以及牺牲电池栅极堆叠周围形成间隔层。然后去除牺牲单元栅极堆叠，使得牺牲单元栅极堆叠周围的间隔层仍然完整。 BJT电池堆随后形成在形成和去除牺牲电池栅极堆叠的间隔层之间的空间中，BJT电池堆包括发射极层。然后形成发射极上方的相变层和相变层上方的电极。

86. 发明授权

US07639527B2 Phase change memory dynamic resistance test and manufacturing methods 有权
标题翻译：相变记忆动态电阻测试及制造方法
公开(公告)号：US07639527B2
公开(公告)日：2009-12-29
申请号：US11970348
申请日：2008-01-07
申请人： Ming-Hsiu Lee , Bipin Rajendran , Chung Hon Lam
发明人： Ming-Hsiu Lee , Bipin Rajendran , Chung Hon Lam
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C13/0004 , G11C29/50008 , Y10T29/49004
摘要： A method for testing an integrated circuit memory device includes applying a sequence of test pulses to a memory cell on the device, where the test pulses result in current through the memory cell having an amplitude dependent on the test pulse. Resistance in the memory cell is measured in response to the sequence of test pulses. A parameter set is extracted from the resistance measurements which includes at least one numerical coefficient that models dependency of the measured resistance on the amplitude of the current through the memory cell. The extracted numerical coefficient or coefficients are associated with the memory device, and used for controlling manufacturing operations.
摘要翻译：用于测试集成电路存储器件的方法包括将测试脉冲序列应用于器件上的存储器单元，其中测试脉冲导致具有取决于测试脉冲的幅度的存储器单元的电流。响应于测试脉冲的顺序测量存储器单元中的电阻。从电阻测量中提取参数集，其包括至少一个数值系数，其模拟所测量的电阻对通过存储器单元的电流的振幅的依赖性。提取的数值系数或系数与存储器件相关联，并用于控制制造操作。

87. 发明授权

US08832011B2 Electronic synapses from stochastic binary memory devices 有权
公开(公告)号：US08832011B2
公开(公告)日：2014-09-09
申请号：US13611722
申请日：2012-09-12
申请人： Bipin Rajendran , Mark B. Ritter
发明人： Bipin Rajendran , Mark B. Ritter
IPC分类号： G06N3/04 , G06N3/00 , G06N3/063
CPC分类号： G06N3/0635 , G06N3/04 , G06N3/049
摘要： According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.

88. 发明申请

US20140078837A1 COMPACT LOW-POWER ASYNCHRONOUS RESISTOR-BASED MEMORY READ OPERATION AND CIRCUIT 有权
标题翻译：紧凑型低功耗异步电动势记忆读取操作和电路
公开(公告)号：US20140078837A1
公开(公告)日：2014-03-20
申请号：US13552932
申请日：2012-07-19
申请人： SEONGWON KIM , Yong Liu , Bipin Rajendran
发明人： SEONGWON KIM , Yong Liu , Bipin Rajendran
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C7/067 , G11C11/5678 , G11C13/0004
摘要： A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.
摘要翻译：紧凑型低功率异步电阻器存储器读取电路包括具有多个连续存储器状态的存储单元，每个所述状态对应于相应的输出电压。读出放大器读取存储单元的状态。感测放大器包括分压器，其被配置为接收存储器单元的输出电压并且输出稳定电压，放大器具有在与所述连续存储器状态中的两个相关联的稳定电压之间的电压阈值，其被配置为区分所述两个连续存储器状态。

89. 发明申请

US20120084240A1 PHASE CHANGE MEMORY SYNAPTRONIC CIRCUIT FOR SPIKING COMPUTATION, ASSOCIATION AND RECALL 审中-公开
标题翻译：相位改变记忆同步电路，用于SPIKING计算，协调和调用
公开(公告)号：US20120084240A1
公开(公告)日：2012-04-05
申请号：US12895710
申请日：2010-09-30
申请人： Steven K. Esser , Dharmendra S. Modha , Anthony Ndirango , Bipin Rajendran
发明人： Steven K. Esser , Dharmendra S. Modha , Anthony Ndirango , Bipin Rajendran
IPC分类号： G06N3/04
CPC分类号： G06N3/063
摘要： Embodiments of the invention are directed to producing spike-timing dependent plasticity using electronic neurons for computation, and pattern matching tasks such as association and recall. In response to an electronic neuron spiking, a spiking signal is sent from the electronic neuron to each axon driver and each dendrite driver connected to the spiking electronic neuron. Each axon driver receiving the spiking signal sends an axonal signal from the axon driver to a variable state resistor. Each dendrite driver receiving the spiking signal sends a dendritic signal from the dendrite driver to the variable state resistor, wherein the variable state resistor couples the axon driver and the dendrite driver. The combination of the axonal and dendritic signals is capable of increasing or decreasing conductance of the variable state resistor.
摘要翻译：本发明的实施例涉及使用用于计算的电子神经元和诸如关联和召回的模式匹配任务来产生尖峰时序相关的可塑性。响应于电子神经元峰值，从电子神经元发送尖峰信号到每个轴突驱动器，并且每个枝晶驱动器连接到尖峰电子神经元。接收尖峰信号的每个轴突驱动器将轴突信号从轴突驱动器发送到可变状态电阻器。接收尖峰信号的每个枝晶驱动器将枝晶信号从枝晶驱动器发送到可变状态电阻器，其中可变状态电阻器耦合轴突驱动器和枝晶驱动器。轴突和树突状信号的组合能够增加或降低可变状态电阻的电导。

90. 发明申请

US20110153533A1 PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN AN ULTRA-DENSE SYNAPSE CROSS-BAR ARRAY 有权
标题翻译：在超声波同步串联阵列阵列中产生依赖时间的塑性
公开(公告)号：US20110153533A1
公开(公告)日：2011-06-23
申请号：US12645479
申请日：2009-12-22
申请人： Bryan Lawrence Jackson , Dharmendra Shantilal Modha , Bipin Rajendran
发明人： Bryan Lawrence Jackson , Dharmendra Shantilal Modha , Bipin Rajendran
IPC分类号： G06N3/02
CPC分类号： G06N3/049 , G06N3/0635
摘要： Embodiments of the invention relate to producing spike-timing dependent plasticity in an ultra-dense synapse cross-bar array for neuromorphic systems. An aspect of the invention includes when an electronic neuron spikes, an alert pulse is sent from the spiking electronic neuron to each electronic neuron connected to the spiking electronic neuron. When the spiking electronic neuron sends the alert pulse, a gate pulse is sent from the spiking electronic neuron to each electronic neuron connected to the spiking electronic neuron. When each electronic neuron receives the alert pulse, a response pulse is sent from each electronic neuron receiving the alert pulse to the spiking electronic neuron. The response pulse is a function of time since a last spiking of the electronic neuron receiving the alert pulse. In addition, the combination of the gate pulse and response pulse is capable increasing or decreasing conductance of a variable state resistor.
摘要翻译：本发明的实施方案涉及在用于神经形态系统的超密集突触交叉阵列中产生尖峰时间依赖性可塑性。本发明的一个方面包括当电子神经元尖峰时，警报脉冲从尖峰电子神经元发送到连接到尖峰电子神经元的每个电子神经元。当尖峰电子神经元发出警报脉冲时，门脉冲从尖峰电子神经元发送到连接到尖峰电子神经元的每个电子神经元。当每个电子神经元接收到警报脉冲时，从接收警报脉冲的每个电子神经元发送响应脉冲到尖峰电子神经元。响应脉冲是从接收警报脉冲的电子神经元的最后一次尖峰起的时间的函数。此外，门脉冲和响应脉冲的组合能够增加或降低可变状态电阻器的电导。

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