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82. 发明申请

US20070200604A1 DELAY LOCKED LOOP APPARATUS 有权
标题翻译：延迟锁定环路设备
公开(公告)号：US20070200604A1
公开(公告)日：2007-08-30
申请号：US11677619
申请日：2007-02-22
申请人： Won Joo YUN , Hyun Woo LEE
发明人： Won Joo YUN , Hyun Woo LEE
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0818 , H03L7/087
摘要： The present invention relates to a delay locked loop (DLL) apparatus. The DLL apparatus includes: a first delay means converting a reference clock into a rising clock; a second delay means converting the reference clock into a falling clock by delaying the reference clock; a replica delay unit replica-delaying the rising clock delayed by the first delay means; a first phase detection means comparing the phases of the reference clock and the delayed rising clock to output a first detection signal corresponding to the compared phases; a control means synchronizing the rising edge of the rising clock with the rising edge of the reference clock in accordance with the first detection signal of the first phase detection means; and a second phase detection means comparing the phases of the rising clock synchronized by the control means and the synchronization clock to output a second detection signal corresponding to the compared phases. Accordingly, there is provided a DLL apparatus for compensating for a skew between an external clock and data and between external and internal clocks by employing a single replica delay unit.
摘要翻译：延迟锁定环（DLL）装置技术领域本发明涉及延迟锁定环（DLL）装置。 DLL装置包括：将参考时钟转换为上升时钟的第一延迟装置; 第二延迟装置通过延迟参考时钟将参考时钟转换成下降时钟; 复制延迟单元复制延迟由第一延迟装置延迟的上升时钟; 第一相位检测装置，比较参考时钟和延迟上升时钟的相位，以输出对应于所比较的相位的第一检测信号; 控制装置根据第一相位检测装置的第一检测信号使上升时钟的上升沿与基准时钟的上升沿同步; 以及第二相位检测装置，比较由控制装置同步的上升时钟的相位和同步时钟，以输出对应于比较相位的第二检测信号。因此，提供了一种DLL装置，用于通过采用单个复制延迟单元来补偿外部时钟和数据之间以及外部和内部时钟之间的偏斜。

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