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81. 发明授权

US5766970A Method of manufacturing a twin well semiconductor device with improved planarity 失效
标题翻译：具有改善的平面性的制造双阱半导体器件的方法
公开(公告)号：US5766970A
公开(公告)日：1998-06-16
申请号：US22637
申请日：1993-02-25
申请人： Young-Pil Kim , Tae-Young Chung
发明人： Young-Pil Kim , Tae-Young Chung
IPC分类号： H01L21/8238 , H01L21/8239 , H01L21/8242 , H01L27/092 , H01L27/10 , H01L27/108 , H01L21/70 , H01L21/302 , H01L21/76 , H01L27/00
CPC分类号： H01L21/823892 , H01L27/1052 , Y10S438/96
摘要： A method for manufacturing semiconductor devices having a twin well structure in which the N-well and P-well regions of the substrate receive differential processing to set the final planarity of the semiconductor device. The differential processing permits the relative vertical position of the N-well and P-well surfaces to be controlled as needed to reduce the demands on subsequent processing steps. The relative vertical position of the N-well and P-well surfaces are preferentially set to improve the planarity of the semiconductor device during subsequent manufacturing processes, particularly photolithographic and metallization processes.
摘要翻译：一种用于制造具有双阱结构的半导体器件的方法，其中衬底的N阱和P阱区域接收差分处理以设置半导体器件的最终平坦度。微分处理允许根据需要控制N阱和P阱表面的相对垂直位置以减少对后续处理步骤的要求。优选地设置N阱和P阱表面的相对垂直位置以改善在后续制造工艺，特别是光刻和金属化工艺中半导体器件的平面性。

82. 发明授权

US5378908A Stack capacitor DRAM cell having increased capacitor area 失效
标题翻译：堆叠电容器DRAM单元具有增加的电容器面积
公开(公告)号：US5378908A
公开(公告)日：1995-01-03
申请号：US283968
申请日：1988-12-13
申请人： Dae-Je Chin , Tae-Young Chung
发明人： Dae-Je Chin , Tae-Young Chung
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/92
CPC分类号： H01L27/10852 , H01L27/10808
摘要： A saddled and wrapped stack capacitor DRAM and a method thereof are provided. The DRAM of the invention includes three factors in increasing the effective area for a capacitor. One is a storage poly layer comprising a first poly layer and a second poly layer, which is formed thick in a region over a field oxide layer through two steps; another is a spacer which is formed through an etchback technique for an oxide layer coated on another oxide layer being patterened to selectively remove the storage poly layer, and the spacer maximizes the size of the storage poly; another is an undercut which is formed in boundary regions on an upper oxide layer, on which a plat poly material is coated and wrapped.
摘要翻译：提供了一种叠置和堆叠的堆叠电容器DRAM及其方法。本发明的DRAM包括增加电容器有效面积的三个因素。一种是存储多层，其包括第一多晶层和第二多晶硅层，其通过两个步骤在场氧化物层上的区域中形成为厚; 另一个是通过蚀刻技术形成的间隔物，其中涂覆在另一氧化物层上的氧化物层被选择性地选择性地去除存储多晶硅层，并且间隔物使存储聚硅的尺寸最大化; 另一种是在上氧化物层上的边界区域上形成底切，在其上涂覆和包裹平板状多层材料。

83. 发明授权

US11618536B2 Heat-insulating structural material, and low temperature and ultra-low temperature liquefied gas carrier using the same 有权
公开(公告)号：US11618536B2
公开(公告)日：2023-04-04
申请号：US16646531
申请日：2018-09-05
申请人： Tae Young Chung
发明人： Tae Young Chung , Kong Ju Park
IPC分类号： E04C1/00 , B63B73/20 , B32B3/06 , B32B3/08 , B32B7/08 , B32B15/095 , B32B15/18 , B32B27/40 , E04B1/76 , E04B1/80 , E04C2/292 , F17C3/08 , B63B25/16
摘要： The present invention relates to a heat-insulating structural material, which: firstly, can minimize or prevent a thermal bridge by improving the structure of the connection part of the heat-insulating structural material; secondly, improves insulation performance by arranging a vacuum insulation material inside the core layer of the heat-insulating structural material; and thirdly, increases structural stiffness by forming the core layer from a non-foaming polymer material having excellent structural performance, prevents gas from moving in or out of the vacuum insulation material through the air-tight adhesive structure of the core layer, and can improve fire protection performance so as not to be vulnerable to fire, and thus the present invention is universally applicable to fields requiring insulation ability and structural performance.

84. 发明申请

US20150138684A1 ELECTRIC CIRCUIT BREAKER CAPABLE OF CIRCUIT-BREAKING WHEN DETECTING ARC AND OVER-LOAD 审中-公开
标题翻译：检测电弧和过载电路时可断电的电路断路器
公开(公告)号：US20150138684A1
公开(公告)日：2015-05-21
申请号：US14402690
申请日：2013-05-24
申请人： Tae Young Chung , Dea Sang Kim
发明人： Tae Young Chung , Dea Sang Kim
IPC分类号： H02H3/08 , H02H3/02 , H02H1/00 , H02H3/093
CPC分类号： H02H1/0015 , H02H3/093
摘要： Disclosed is a power off device which includes a micro arc detector for turning on a first switching element, based on a voltage induced in a high frequency choke coil by a high frequency pulse current caused by micro arc at a power line, a high current arc detector for outputting a high current arc detection current during turning-on of a second switching element made based on variation of a magnetic field generated at a coil, a delay unit for accumulatively charging the micro arc detection current or the high current arc detection current in a delay capacitor at a predetermined time constant, a power off unit for electrically disconnecting a load from the power line when an operating voltage is applied, and a first switch for connecting the operating voltage to the power off unit in response to the arc detection signal.
摘要翻译：公开了一种断电装置，其包括微电弧检测器，用于基于在高频扼流线圈中感应的电压，通过由电弧上的微弧引起的高频脉冲电流来接通第一开关元件，高电流电弧检测器，用于在基于线圈产生的磁场的变化产生的第二开关元件的导通期间输出高电流电弧检测电流，用于对微弧检测电流或高电流电弧检测电流进行累积充电的延迟单元延迟电容器，预定时间常数的延迟电容器;用于在施加工作电压时将负载与所述电力线电气断开的断电单元，以及响应于所述电弧检测信号将所述工作电压连接到所述断电单元的第一开关。

85. 发明申请

US20140103482A1 SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNELS AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：具有垂直通道的半导体器件及其制造方法
公开(公告)号：US20140103482A1
公开(公告)日：2014-04-17
申请号：US14109517
申请日：2013-12-17
申请人： Yong-Sung Kim , Tae-Young CHUNG , Soo-Ho SHIN
发明人： Yong-Sung Kim , Tae-Young CHUNG , Soo-Ho SHIN
IPC分类号： H01L29/06 , H01L27/088
CPC分类号： H01L21/28123 , H01L21/76224 , H01L27/088 , H01L27/0886 , H01L27/10826 , H01L27/10879 , H01L29/0649 , H01L29/0653 , H01L29/4238 , H01L29/66795 , H01L29/7802 , H01L29/7827 , H01L29/785 , H01L29/7851 , H01L29/7853
摘要： A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
摘要翻译：一种制造半导体器件的方法，该半导体器件能够防止由有源区的长轴与元件隔离层相交的栅电极引起的泄漏电流，并且还具有垂直沟道以提供足够的重叠余量;以及使用上述制造的半导体器件方法。该器件包括形成在元件隔离层上的栅电极，它们设置在有源区之间并具有高于有源区顶表面的顶表面。由于栅电极形成在元件隔离层上，所以防止了半导体衬底中的漏电流。此外，使用条纹形掩模图案形成栅电极，从而与接触形状或条形图案相比获得足够的重叠余量。

86. 发明授权

US08563373B2 Semiconductor device having vertical channels and method of manufacturing the same 有权
公开(公告)号：US08563373B2
公开(公告)日：2013-10-22
申请号：US12548219
申请日：2009-08-26
申请人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
发明人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
IPC分类号： H01L21/338
CPC分类号： H01L21/28123 , H01L21/76224 , H01L27/088 , H01L27/0886 , H01L27/10826 , H01L27/10879 , H01L29/0649 , H01L29/0653 , H01L29/4238 , H01L29/66795 , H01L29/7802 , H01L29/7827 , H01L29/785 , H01L29/7851 , H01L29/7853
摘要： A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

87. 发明申请

US20130134915A1 CONTROL METHOD OF HYBRID VEHICLE 有权
标题翻译：混合动力车辆的控制方法
公开(公告)号：US20130134915A1
公开(公告)日：2013-05-30
申请号：US13536261
申请日：2012-06-28
申请人： Tae Young Chung , Byunghoon Yang , Jooyoung Park , Hyung Bin Ihm
发明人： Tae Young Chung , Byunghoon Yang , Jooyoung Park , Hyung Bin Ihm
IPC分类号： H02P6/16
CPC分类号： B60L15/20 , H02P21/50 , H02P29/02 , Y02T10/643 , Y02T10/645 , Y02T10/7275
摘要： A control method of a vehicle having a motor according to an exemplary embodiment of the present invention can include confirming that a speed of the motor is not 0 and an output torque thereof is 0 in a condition that the vehicle is being operated, confirming that a voltage of the motor converges to a regular value, and accumulating control data for the motor and processing the control data to calculate an offset value of a resolver. Accordingly, the control method of a vehicle effectively determines whether the offset of the resolver is to be compensated without affecting the drivability of the vehicle.
摘要翻译：具有根据本发明的示例性实施例的电动机的车辆的控制方法可以包括在车辆被操作的条件下确认电动机的速度不为0并且其输出转矩为0，确认电机的电压收敛到常规值，并且积累电机的控制数据并处理控制数据以计算旋转变压器的偏移值。因此，车辆的控制方法有效地确定在不影响车辆驾驶性能的情况下是否补偿旋转变压器的偏移。

88. 发明授权

US08101515B2 Methods of manufacturing semiconductor devices having contact plugs in insulation layers 有权
标题翻译：制造在绝缘层中具有接触插塞的半导体器件的方法
公开(公告)号：US08101515B2
公开(公告)日：2012-01-24
申请号：US12766137
申请日：2010-04-23
申请人： Joon-ho Sung , Ju-yong Lee , Mi-kyung Park , Tae-young Chung
发明人： Joon-ho Sung , Ju-yong Lee , Mi-kyung Park , Tae-young Chung
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/60 , H01L21/74 , H01L21/8238 , H01L21/8234 , H01L21/8242 , H01L21/20
CPC分类号： H01L21/76897 , H01L21/76885 , H01L27/10855 , H01L27/10885 , H01L27/10888
摘要： Methods of manufacturing semiconductor devices are provided in which a first contact plug is formed on a first active region in a substrate and a second contact plug is formed on a second active region in the substrate. A height of an upper surface of the second contact plug from the substrate is greater than a height of an upper surface of the first contact plug from the substrate. A third contact plug is formed on the second contact plug. A first spacer is formed on a side surface of the third contact plug. A third interlayer insulation layer is formed that covers the third contact plug. The third interlayer insulation layer is patterned to form a third opening that exposes the first contact plug. A fourth contact plug is formed in the third opening that is electrically connected to the first contact plug.
摘要翻译：提供制造半导体器件的方法，其中第一接触插塞形成在衬底中的第一有源区上，并且第二接触插塞形成在衬底中的第二有源区上。第二接触塞从基板的上表面的高度大于第一接触塞从基板的上表面的高度。在第二接触插塞上形成第三接触插塞。第一间隔件形成在第三接触插塞的侧表面上。形成覆盖第三接触插塞的第三层间绝缘层。图案化第三层间绝缘层以形成暴露第一接触插塞的第三开口。第四接触插塞形成在电连接到第一接触插塞的第三开口中。

89. 发明授权

US07893487B2 Recessed channel transistor 失效
标题翻译：嵌入式沟道晶体管
公开(公告)号：US07893487B2
公开(公告)日：2011-02-22
申请号：US12314582
申请日：2008-12-12
申请人： Jin-Woo Lee , Tae-Young Chung , Joo-Young Lee
发明人： Jin-Woo Lee , Tae-Young Chung , Joo-Young Lee
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66621 , H01L21/26513 , H01L21/823412 , H01L21/823437 , H01L29/1037 , H01L29/105 , H01L29/4236
摘要： A recessed channel transistor includes a single crystalline silicon substrate having a recessed portion, a bottom surface of the recessed portion including an elevated central portion, a channel doping region in the single crystalline silicon substrate, the channel doping region being under the bottom surface of the recessed portion, a gate structure in the recessed portion, and source/drain regions in the single crystalline silicon substrate at both sides of the recessed portion, the source/drain regions being spaced apart from the bottom surface of the recessed portion.
摘要翻译：凹陷沟道晶体管包括具有凹陷部分的单晶硅衬底，凹部的底表面包括升高的中心部分，在单晶硅衬底中的沟道掺杂区域，沟道掺杂区域位于凹陷部分，凹陷部分中的栅极结构以及在凹陷部分两侧的单晶硅衬底中的源极/漏极区域，源极/漏极区域与凹陷部分的底表面间隔开。

90. 发明申请

US20100210087A1 Methods of Manufacturing Semiconductor Devices Having Contact Plugs in Insulation Layers 有权
标题翻译：制造具有接触插头在绝缘层中的半导体器件的方法
公开(公告)号：US20100210087A1
公开(公告)日：2010-08-19
申请号：US12766137
申请日：2010-04-23
申请人： Joon-ho Sung , Ju-yong Lee , Mi-kyung Park , Tae-young Chung
发明人： Joon-ho Sung , Ju-yong Lee , Mi-kyung Park , Tae-young Chung
IPC分类号： H01L21/768 , H01L21/02
CPC分类号： H01L21/76897 , H01L21/76885 , H01L27/10855 , H01L27/10885 , H01L27/10888
摘要： Methods of manufacturing semiconductor devices are provided in which a first contact plug is formed on a first active region in a substrate and a second contact plug is formed on a second active region in the substrate. A height of an upper surface of the second contact plug from the substrate is greater than a height of an upper surface of the first contact plug from the substrate. A third contact plug is formed on the second contact plug. A first spacer is formed on a side surface of the third contact plug. A third interlayer insulation layer is formed that covers the third contact plug. The third interlayer insulation layer is patterned to form a third opening that exposes the first contact plug. A fourth contact plug is formed in the third opening that is electrically connected to the first contact plug.
摘要翻译：提供制造半导体器件的方法，其中第一接触插塞形成在衬底中的第一有源区上，并且第二接触插塞形成在衬底中的第二有源区上。第二接触塞从基板的上表面的高度大于第一接触塞从基板的上表面的高度。在第二接触插塞上形成第三接触插塞。第一间隔件形成在第三接触插塞的侧表面上。形成覆盖第三接触插塞的第三层间绝缘层。图案化第三层间绝缘层以形成暴露第一接触插塞的第三开口。第四接触插塞形成在电连接到第一接触插塞的第三开口中。

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