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81. 发明授权

US08704203B2 Transition metal oxide bilayers 有权
标题翻译：过渡金属氧化物双层
公开(公告)号：US08704203B2
公开(公告)日：2014-04-22
申请号：US13971467
申请日：2013-08-20
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Hieu Pham , Vidyut Gopal , Imran Hashim , Tim Minvielle , Yun Wang , Takeshi Yamaguchi , Hong Sheng Yang
IPC分类号： H01L29/02
CPC分类号： H01L45/08 , H01L27/2409 , H01L27/2463 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1616 , H01L45/1625 , H01L45/1641
摘要： Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 Å and about 100 Å, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.
摘要翻译：本发明的实施例包括非易失性存储器元件和包括非易失性存储元件的存储器件。还公开了形成非易失性存储元件的方法。非易失性存储元件包括第一电极层，第二电极层和设置在第一和第二电极层之间的多个氧化物层。氧化物层中的一个具有线性电阻和亚化学计量组成，另一个氧化物层具有双稳态电阻和近化学计量组成。优选地，两个氧化物层厚度的总和在约和之间，并且具有双稳态电阻的氧化物层具有在总厚度的约25％至约75％之间的厚度。在一个实施例中，氧化物层在具有受控的氩气和氧气的气氛中使用反应溅射形成。

82. 发明申请

US20140103280A1 NONVOLATILE RESISTIVE MEMORY ELEMENT WITH A PASSIVATED SWITCHING LAYER 审中-公开
标题翻译：具有钝化开关层的非易失性电阻记忆元件
公开(公告)号：US20140103280A1
公开(公告)日：2014-04-17
申请号：US14133107
申请日：2013-12-18
申请人： Kabushiki Kaisha Toshiba , SANDISK 3D LLC
发明人： Charlene Chen , Dipankar Pramanik
IPC分类号： H01L45/00
CPC分类号： H01L45/146 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/165
摘要： A nonvolatile resistive memory element has a novel variable resistance layer that is passivated with non-metallic dopant atoms, such as nitrogen, either during or after deposition of the switching layer. The presence of the non-metallic dopant atoms in the variable resistance layer enables the switching layer to operate with reduced switching current while maintaining improved data retention properties.
摘要翻译：非易失性电阻存储元件具有新颖的可变电阻层，其在开关层沉积期间或之后被非金属掺杂剂原子如氮气钝化。可变电阻层中的非金属掺杂剂原子的存在使得开关层能够以降低的开关电流工作，同时保持改进的数据保持性能。

83. 发明授权

US08687410B2 Nonvolatile memory cell comprising a diode and a resistance-switching material 有权
标题翻译：包括二极管和电阻切换材料的非易失性存储单元
公开(公告)号：US08687410B2
公开(公告)日：2014-04-01
申请号：US13734536
申请日：2013-01-04
申请人： SanDisk 3D LLC
发明人： Scott Brad Herner , Christopher J. Petti , Tanmay Kumar
IPC分类号： G11C11/00 , G11C5/02 , G11C5/06
CPC分类号： H01L27/249 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： A method is provided for programming a memory cell in a memory array. The memory cell includes a resistivity-switching layer of a metal oxide or nitride compound, and the metal oxide or nitride compound includes exactly one metal. The method includes programming the memory cell by changing the resistivity-switching layer from a first resistivity state to a second programmed resistivity state, wherein the second programmed resistivity state stores a data state of the memory cell. Numerous other aspects are provided.
摘要翻译：提供了一种用于对存储器阵列中的存储器单元进行编程的方法。存储单元包括金属氧化物或氮化物化合物的电阻率切换层，并且金属氧化物或氮化物化合物仅包括一个金属。该方法包括通过将电阻率切换层从第一电阻率状态改变到第二编程电阻率状态来对存储单元进行编程，其中第二编程电阻率状态存储存储单元的数据状态。提供了许多其他方面。

84. 发明申请

US20140078851A1 CONTINUOUS MESH THREE DIMENSIONAL NON-VOLATILE STORAGE WITH VERTICAL SELECT DEVICES 有权
公开(公告)号：US20140078851A1
公开(公告)日：2014-03-20
申请号：US14089715
申请日：2013-11-25
申请人： Sandisk 3D LLC
发明人： Roy E. Scheuerlein
IPC分类号： G11C13/00
CPC分类号： G11C13/0033 , G11C5/025 , G11C8/08 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C13/0069 , H01L27/0688 , H01L27/115 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/165 , H01L45/1683
摘要： A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

85. 发明授权

US08637389B2 Resist feature and removable spacer pitch doubling patterning method for pillar structures 有权
标题翻译：支柱结构的抗蚀特征和可移除的间隔物间距倍增图案化方法
公开(公告)号：US08637389B2
公开(公告)日：2014-01-28
申请号：US13744971
申请日：2013-01-18
申请人： SanDisk 3D LLC
发明人： Yung-Tin Chen , Steven J. Radigan
IPC分类号： H01L21/3205
CPC分类号： H01L45/1691 , H01L21/0337 , H01L21/0338 , H01L27/1021
摘要： A method of making a memory array is provided that includes forming a layer over a substrate, forming features over the layer, forming sidewall spacers on each of the features, filling spaces between adjacent sidewall spacers with filler features, removing the sidewall spacers to leave the features and the filler features, and etching the layer using the features and the filler features as a mask to form pillar shaped nonvolatile memory cells. Numerous other aspects are provided.
摘要翻译：提供了一种制造存储器阵列的方法，其包括在衬底上形成层，在层上形成特征，在每个特征上形成侧壁间隔物，在填充物特征之间填充相邻侧壁间隔物之间的空间，去除侧壁间隔物，特征和填料特征，并且使用特征和填料特征作为掩模来蚀刻层以形成柱状非易失性存储单元。提供了许多其他方面。

86. 发明申请

US20130336038A1 NON-VOLATILE MEMORY HAVING 3D ARRAY ARCHITECTURE WITH STAIRCASE WORD LINES AND VERTICAL BIT LINES AND METHODS THEREOF 有权
标题翻译：具有STAIRCASE WORD行和垂直位线的3D阵列架构的非易失性存储器及其方法
公开(公告)号：US20130336038A1
公开(公告)日：2013-12-19
申请号：US13840759
申请日：2013-03-15
申请人： SANDISK 3D LLC
发明人： Raul Adrian Cernea , George Samachisa
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： H01L27/249 , G06F12/0238 , G11C5/025 , G11C5/06 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C2213/71 , H01L21/76877 , H01L27/1052 , H01L27/2454 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： In a 3D nonvolatile memory with memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate; a plurality of local bit lines elongated in the z-direction through the plurality of layers and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; the 3D nonvolatile memory further having a plurality of staircase word lines spaced apart in the y-direction and between and separated from the plurality of bit line pillars at a plurality of crossings, individual staircase word lines each having a series of alternating steps and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane.
摘要翻译：在具有以由具有x，y和z方向的直角坐标定义的三维图案中布置的存储元件的3D非易失性存储器中，并且具有多个平行平面，从底平面到在z方向上堆叠的顶平面半导体衬底; 多个局部位线沿Z方向延伸穿过多个层并且布置在具有沿x方向和y方向的列的行的位线柱的二维矩形阵列中; 所述3D非易失性存储器还具有沿着y方向间隔开并且在多个位置处与所述多个位线柱之间和分离的多个阶梯字线，各个阶梯字线各自具有一系列交替的台阶和提升板分别在x方向和z方向上在z方向上跨越多个平面横跨每个平面中的段。

87. 发明申请

US20130286728A1 NONVOLATILE MEMORY CELL OPERATING BY INCREASING ORDER IN POLYCRYSTALLINE SEMICONDUCTOR MATERIAL 有权
标题翻译：通过在多晶半导体材料中增加订单来操作非易失性存储器单元
公开(公告)号：US20130286728A1
公开(公告)日：2013-10-31
申请号：US13925917
申请日：2013-06-25
申请人： SanDisk 3D LLC
发明人： Scott Brad Herner , Abhijit Bandyopadhyay
IPC分类号： G11C11/36
CPC分类号： G11C11/36 , G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , H01L27/1021
摘要： A memory cell is provided that includes a first conductor, a second conductor, and a semiconductor junction diode between the first and second conductors. The semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 12 percent with the semiconductor junction diode. Numerous other aspects are provided.
摘要翻译：提供了一种存储单元，其包括在第一和第二导体之间的第一导体，第二导体和半导体结二极管。半导体结二极管与半导体结二极管不与具有小于12％的晶格失配的材料接触。提供了许多其他方面。

88. 发明授权

US08565015B2 Methods of programming two terminal memory cells 有权
标题翻译：编程两个终端存储单元的方法
公开(公告)号：US08565015B2
公开(公告)日：2013-10-22
申请号：US13765394
申请日：2013-02-12
申请人： SanDisk 3D LLC
发明人： Tyler J. Thorp , Roy E. Scheuerlein
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2013/0092
摘要： Methods of programming two terminal memory cells are provided. A method includes: (a) reading information of a memory page including first, second, and nth memory cells, the information including first, second, and nth program pulse tuning instructions; (b) creating a first program pulse in accordance with the first program pulse tuning instructions to program the first memory cell; (c) locking the first memory cell from further programming pulses; (d) creating a second program pulse in accordance with the second program pulse tuning instructions to program the second memory cell; (e) locking the second memory cell from further programming pulses; and (f) creating an nth program pulse in accordance with the nth program pulse tuning instructions to program the nth memory cell.
摘要翻译：提供了编程两个终端存储单元的方法。一种方法包括：（a）读取包括第一，第二和第n存储器单元的存储器页的信息，该信息包括第一，第二和第N编程脉冲调谐指令; （b）根据第一编程脉冲调谐指令产生第一编程脉冲以对第一存储单元进行编程; （c）锁定所述第一存储器单元以进一步编程脉冲; （d）根据第二编程脉冲调谐指令产生第二编程脉冲以编程第二存储单元; （e）锁定所述第二存储器单元以进一步编程脉冲; 和（f）根据第n个编程脉冲调谐指令产生第n个编程脉冲以对第n个存储单元进行编程。

89. 发明申请

US20130264675A1 APPARATUS FOR FORMING MEMORY LINES AND VIAS IN THREE DIMENSIONAL MEMORY ARRAYS USING DUAL DAMASCENE PROCESS AND IMPRINT LITHOGRAPHY 审中-公开
标题翻译：在使用双重DAMASCENE过程和印刷图形的三维存储器阵列中形成存储器线和VIAS的装置
公开(公告)号：US20130264675A1
公开(公告)日：2013-10-10
申请号：US13911294
申请日：2013-06-06
申请人： SanDisk 3D LLC
发明人： Roy E. Scheuerlein
IPC分类号： H01L21/48 , H01L23/538 , H01L27/10
CPC分类号： H01L21/48 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/31144 , H01L21/76807 , H01L21/76817 , H01L23/5384 , H01L27/10 , H01L27/101 , H01L2221/1021 , H01L2924/0002 , H01L2924/00
摘要： A memory layer in a three-dimensional memory array is provided. The memory layer includes a plurality of memory lines and vias formed by a damascene process using an imprint lithography template having a plurality of depths, wherein at least one depth corresponds to the memory lines and wherein at least one depth corresponds to the vias, and a plurality of memory cells operatively coupled to the memory lines. Numerous other aspects are disclosed.
摘要翻译：提供三维存储器阵列中的存储器层。存储层包括多个存储线和通过使用具有多个深度的压印光刻模板的镶嵌工艺形成的通孔，其中至少一个深度对应于存储器线，并且其中至少一个深度对应于通孔，并且多个可操作地耦合到存储器线的存储单元。公开了许多其他方面。

90. 发明申请

US20130164921A1 HIGH-DENSITY NONVOLATILE MEMORY AND METHODS OF MAKING THE SAME 有权
标题翻译：高密度非易失性存储器及其制造方法
公开(公告)号：US20130164921A1
公开(公告)日：2013-06-27
申请号：US13776193
申请日：2013-02-25
申请人： SanDisk 3D LLC
发明人： Scott Brad Herner , Maitreyee Mahajani
IPC分类号： H01L21/02
CPC分类号： G11C5/02 , H01L21/8238 , H01L23/48 , H01L27/1021 , H01L27/148 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： Methods are provided for forming a monolithic three dimensional memory array. An example method includes: (a) forming a first plurality of substantially parallel, substantially coplanar conductors above a substrate; (b) forming a first plurality of semiconductor elements above the first plurality of substantially parallel, substantially coplanar conductors; and (c) forming a second plurality of substantially parallel, substantially coplanar conductors above the first plurality of semiconductor elements. Each of the first plurality of semiconductor elements includes a first heavily doped layer having a first conductivity type, a second lightly doped layer on and in contact with the first heavily doped layer, and a third heavily doped layer on and in contact with the second lightly doped layer. The third heavily doped layer has a second conductivity type opposite the first conductivity type. Numerous other aspects are provided.
摘要翻译：提供了用于形成单片三维存储器阵列的方法。一种示例性方法包括：（a）在衬底上方形成第一多个基本平行的基本共面的导体; （b）在所述第一多个基本平行的基本上共面的导体上形成第一多个半导体元件; 以及（c）在所述第一多个半导体元件上方形成第二多个基本平行的基本共面的导体。第一多个半导体元件中的每一个包括具有第一导电类型的第一重掺杂层，在第一重掺杂层上并与第一重掺杂层接触的第二轻掺杂层，以及与第二重掺杂层接触的第三重掺杂层掺杂层。第三重掺杂层具有与第一导电类型相反的第二导电类型。提供了许多其他方面。

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