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    • 89. 发明申请
    • CRT vertical scanning circuit with a low power standby
    • CRT垂直扫描电路具有低功耗待机
    • US20040257008A1
    • 2004-12-23
    • US10812843
    • 2004-03-30
    • STMicroelectronics S.A.
    • Jean-Michel Moreau
    • G09G001/04
    • H04N3/16
    • The invention concerns a scanning circuit, comprising a power supply providing a negative voltage on a first terminal (Tdown), an intermediate voltage on a second terminal (Gnd) and a positive voltage on a terminal of a switch (S), the other terminal of the switch being connected to a third terminal (Tup), a control circuit (6) supplied by connections to the second and third terminals, a differential amplifier receiving a positive and a negative input signal provided by the control circuit, a power amplifier controlled by the differential amplifier, both amplifiers being supplied by connections to the first and third terminals, a deflection coil (Ly) connected between the output of the power amplifier and the second terminal, biasing means setting, when the switch is open, the output of the differential amplifier so that the possible current paths through the power amplifier between the deflection coil and the first terminal are cut.
    • 本发明涉及一种扫描电路,包括在第一端子(Tdown)上提供负电压的电源,第二端子上的中间电压(Gnd)和开关(S)的端子上的正电压,另一个端子 所述开关连接到第三端子(Tup),通过连接到所述第二和第三端子提供的控制电路(6),接收由所述控制电路提供的正和负输入信号的差分放大器,控制的功率放大器 通过差分放大器,通过连接到第一和第三端子的两个放大器提供连接在功率放大器的输出端和第二端子之间的偏转线圈(Ly),当开关断开时,偏置装置设定输出 差分放大器,使得穿过偏转线圈和第一端子之间的功率放大器的可能电流路径被切断。
    • 90. 发明申请
    • Cache cell with masking
    • 具有掩蔽的缓存单元
    • US20040252536A1
    • 2004-12-16
    • US10862057
    • 2004-06-04
    • STMicroelectronics S.A.
    • Richard Ferrant
    • G11C027/00
    • G11C15/04
    • A CAM cell with masking made in the form of an integrated circuit, including a first storage cell including a first transistor, first and second inverters in anti-parallel, and a second transistor; a comparison cell, including third and fourth transistors controlling a fifth transistor, connected in series with a sixth inhibiting transistor to a result line; and a second storage cell, including a seventh transistor in series with two inverters in anti-parallel and an eighth transistor, the second storage cell controlling the inhibiting transistor. The first, second, seventh, and eighth transistors may be N-channel transistors, and the third, fourth, fifth, and sixth transistors may be P-channel transistors.
    • 具有以集成电路形式形成的掩蔽的CAM单元,包括:第一存储单元,包括第一晶体管,反并联的第一和第二反相器以及第二晶体管; 比较单元,包括控制第五晶体管的第三和第四晶体管,与第六抑制晶体管串联连接到结果行; 以及第二存储单元,其包括与反并联的两个反相器串联的第七晶体管和第八晶体管,所述第二存储单元控制所述抑制晶体管。 第一,第二,第七和第八晶体管可以是N沟道晶体管,并且第三,第四,第五和第六晶体管可以是P沟道晶体管。