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81. 发明申请

US20120198133A1 ELECTRONIC DEVICE WITH EXPANDABLE MEMORY CAPACITY AND AN EXPANSION METHOD THEREOF 审中-公开
标题翻译：具有可扩展记忆容量的电子设备及其扩展方法
公开(公告)号：US20120198133A1
公开(公告)日：2012-08-02
申请号：US13191464
申请日：2011-07-27
申请人： CHENG-HAO CHOU , CHIH-SAN CHIANG , MING-TSUNG CHEN
发明人： CHENG-HAO CHOU , CHIH-SAN CHIANG , MING-TSUNG CHEN
IPC分类号： G06F12/02
CPC分类号： G06F12/0623
摘要： An electronic device includes a processor, an internal memory for storing system information and installing programs, and a memory expansion interface for connecting an expansion memory. The expansion memory is partitioned into at least one region to expand the internal memory. The internal memory is partitioned into a system region and a user region; the system region is used to store system information while the user region can be controlled and used by a user. The processor further includes a detection unit and a memory management unit. The detection unit detects the connection of the expansion memory to the memory expansion interface, and the memory management unit determines whether the expansion memory has been previously configured to expand the internal memory, and if not, the memory management unit associates the expansion memory with the internal memory to expand the internal memory.
摘要翻译：电子设备包括处理器，用于存储系统信息的内部存储器和安装程序，以及用于连接扩展存储器的存储器扩展接口。扩展存储器被分割成至少一个区域以扩展内部存储器。内部存储器被划分为系统区域和用户区域; 系统区域用于存储系统信息，而用户区域可以由用户控制和使用。处理器还包括检测单元和存储器管理单元。检测单元检测扩展存储器与存储器扩展接口的连接，并且存储器管理单元确定扩展存储器是否已经被预先配置为扩展内部存储器，如果不是扩展存储器，则存储器管理单元将扩展存储器与内部存储器来扩展内部存储器。

82. 发明申请

US20110143511A1 Method of fabricating n-channel metal-oxide semiconductor transistor 有权
标题翻译：制造n沟道金属氧化物半导体晶体管的方法
公开(公告)号：US20110143511A1
公开(公告)日：2011-06-16
申请号：US12636788
申请日：2009-12-14
申请人： I-Chang Wang , Ling-Chun Chou , Ming-Tsung Chen
发明人： I-Chang Wang , Ling-Chun Chou , Ming-Tsung Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/7834 , H01L29/665 , H01L29/66628
摘要： A method of fabricating an NMOS transistor, in which, an epitaxial silicon layer is formed before a salicide process is performed, then a nickel layer needed for the salicide process is formed, and, thereafter, a rapid thermal process is performed to allow the nickel layer to react with the epitaxial silicon layer and the silicon substrate under the epitaxial silicon layer to form a nickel silicide layer.
摘要翻译：一种制造NMOS晶体管的方法，其中在执行自对准硅化处理之前形成外延硅层，然后形成自对准硅化物处理所需的镍层，然后进行快速热处理，以使镍层，以在外延硅层下与外延硅层和硅衬底反应以形成硅化镍层。

83. 发明授权

US07384853B2 Method of performing salicide processes on MOS transistors 有权
标题翻译：在MOS晶体管上执行自对准硅化物处理的方法
公开(公告)号：US07384853B2
公开(公告)日：2008-06-10
申请号：US11161990
申请日：2005-08-25
申请人： Ming-Tsung Chen , Chang-Chi Huang , Po-Chao Tsao
发明人： Ming-Tsung Chen , Chang-Chi Huang , Po-Chao Tsao
IPC分类号： H01L21/331
CPC分类号： H01L21/28518 , H01L21/26506 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/7834
摘要： A method of performing salicide processes on a MOS transistor, wherein the MOS transistor comprises a gate structure and a source/drain region, the method comprising: performing a selective growth process to form a silicon layer on the top of the gate and the source/drain region; performing an ion implantation process to form a retarded interface layer between the silicon layer and the gate and source/drain region; forming a metal layer on the silicon layer; and reacting the metal layer with the silicon layer for forming a silicide layer.
摘要翻译：一种在MOS晶体管上执行自对准硅化物工艺的方法，其中所述MOS晶体管包括栅极结构和源极/漏极区域，所述方法包括：执行选择性生长工艺以在所述栅极的顶部上形成硅层，并且所述源/ 漏区; 执行离子注入工艺以在硅层和栅极和源极/漏极区之间形成延迟界面层; 在所述硅层上形成金属层; 并使金属层与用于形成硅化物层的硅层反应。

84. 发明申请

US20070166936A1 PRE-AMORPHIZATION IMPLANTATION PROCESS AND SALICIDE PROCESS 审中-公开
标题翻译：预处理植入过程和杀真菌过程
公开(公告)号：US20070166936A1
公开(公告)日：2007-07-19
申请号：US11307008
申请日：2006-01-19
申请人： Po-Chao Tsao , Yi-Yiing Chiang , Chang-Chi Huang , Hsin-Hui Hsu , Ming-Tsung Chen , Chien-Ting Lin
发明人： Po-Chao Tsao , Yi-Yiing Chiang , Chang-Chi Huang , Hsin-Hui Hsu , Ming-Tsung Chen , Chien-Ting Lin
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L29/665 , H01L29/6659
摘要： A salicide process is described, wherein a substrate with an NMOS transistor and a PMOS transistor thereon is provided. A mask layer is formed over the substrate covering the PMOS transistor but exposing the NMOS transistor, and then a pre-amorphization implantation (PAI) step is conducted to the substrate using the mask layer as a mask. After the mask layer is removed, a salicide layer is formed on the NMOS transistor and the PMOS transistor.
摘要翻译：描述了自对准硅化物工艺，其中提供了具有NMOS晶体管和PMOS晶体管的衬底。在覆盖PMOS晶体管的衬底上形成掩模层，但暴露NMOS晶体管，然后使用掩模层作为掩模将前非晶化注入（PAI）步骤传导到衬底。在去除掩模层之后，在NMOS晶体管和PMOS晶体管上形成自对准硅层。

85. 发明申请

US20070082489A1 METHOD OF FABRICATING OPENINGS AND CONTACT HOLES 有权
标题翻译：制作开口和接触孔的方法
公开(公告)号：US20070082489A1
公开(公告)日：2007-04-12
申请号：US11163149
申请日：2005-10-06
申请人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen
发明人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/76802 , H01L21/76831
摘要： A substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer is then patterned to form a plurality of openings exposing the etch stop layer. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the etch stop layer. The dielectric thin film disposed on the dielectric layer and the etch stop layer is then removed.
摘要翻译：提供具有蚀刻停止层和至少从底部到顶部设置的电介质层的衬底。然后将电介质层图案化以形成露出蚀刻停止层的多个开口。随后形成介电薄膜以覆盖电介质层，开口的侧壁和蚀刻停止层。然后去除设置在电介质层和蚀刻停止层上的电介质薄膜。

86. 发明申请

US20070054481A1 SEMICONDUCTOR DEVICE HAVING NICKEL SILICIDE AND METHOD OF FABRICATING NICKEL SILICIDE 有权
标题翻译：具有尼龙硅胶的半导体器件及其制造方法
公开(公告)号：US20070054481A1
公开(公告)日：2007-03-08
申请号：US11162360
申请日：2005-09-08
申请人： Yi-Wei Chen , Chao-Ching Hsieh , Yi-Yiing Chiang , Tzung-Yu Hung , Yu-Lan Chang , Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen
发明人： Yi-Wei Chen , Chao-Ching Hsieh , Yi-Yiing Chiang , Tzung-Yu Hung , Yu-Lan Chang , Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen
IPC分类号： H01L21/28
CPC分类号： H01L29/665 , H01L21/324 , H01L29/4933
摘要： A semiconductor device having nickel suicide and a method for fabricating nickel silicide. A semiconductor substrate having a plurality of doped regions is provided. Subsequently, a nickel layer is formed on the semiconductor substrate, and a first rapid thermal process (RTP) is performed to react the nickel layer with the doped regions disposed thereunder. Thereafter, the unreacted nickel layer is removed, and a second rapid thermal process is performed to form a semiconductor device having nickel silicide. The second rapid thermal process is a spike anneal process whose process temperature is between 400 and 600° C.
摘要翻译：一种具有镍硅化物的半导体器件和一种制造硅化镍的方法。提供具有多个掺杂区域的半导体衬底。接着，在半导体基板上形成镍层，进行第一快速热处理（RTP），使镍层与配置在其上的掺杂区域反应。此后，除去未反应的镍层，进行第二快速热处理以形成具有硅化镍的半导体器件。第二快速热处理是工艺温度在400和600℃之间的尖峰退火工艺。

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