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81. 发明授权

US06331480B1 Method to improve adhesion between an overlying oxide hard mask and an underlying low dielectric constant material 有权
标题翻译：提高上覆氧化物硬掩模与下层低介电常数材料之间粘合力的方法
公开(公告)号：US06331480B1
公开(公告)日：2001-12-18
申请号：US09252469
申请日：1999-02-18
申请人： Chia-Shiung Tsai , Yao-Yi Cheng , Hun-Jan Tao
发明人： Chia-Shiung Tsai , Yao-Yi Cheng , Hun-Jan Tao
IPC分类号： H01L214763
CPC分类号： H01L21/0337 , H01L21/31144 , H01L21/76826 , H01L21/76828 , H01L21/76831
摘要： A method for improving the adhesion, between an overlying insulator layer, and an underlying low K layer, used for forming a composite layer, damascene mask pattern, wherein the damascene mask pattern is used as an interlevel dielectric layer, between metal interconnect structures, has been developed. A treatment, comprised of aqueous NH4OH solutions, or of UV curing procedures, is performed on the top surface of the low K layer, prior to deposition of the overlying insulator layer. The treatment, resulting in a roughened top surface of the low K layer, allows removal of masking photoresist shapes, to be aggressively accomplished using wet strippers, without adhesion loss at the insulator—low K layer interface.
摘要翻译：在金属互连结构之间用于改善用于形成复合层的上覆绝缘体层和下层低K层之间的附着力的方法，其中镶嵌掩模图案用作层间绝缘层，镶嵌掩模图案具有已经开发在沉积上层绝缘体层之前，在低K层的顶表面上进行由NH 4 OH水溶液组成或UV固化程序的处理。导致低K层的粗糙顶表面的处理允许去除掩模光致抗蚀剂形状，使用湿剥离剂积极地实现，而在绝缘体低K层界面处没有粘附损失。

82. 发明授权

US06319822B1 Process for forming an integrated contact or via 有权
标题翻译：用于形成集成接触或通孔的工艺
公开(公告)号：US06319822B1
公开(公告)日：2001-11-20
申请号：US09164999
申请日：1998-10-01
申请人： Chao-Cheng Chen , Chia-Shiung Tsai , Shau-Lin Shue , Hun-Jan Tao
发明人： Chao-Cheng Chen , Chia-Shiung Tsai , Shau-Lin Shue , Hun-Jan Tao
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/0332 , H01L21/0335 , H01L21/31116 , H01L21/31122 , H01L21/31144 , H01L21/76802
摘要： A method for etching of sub-quarter micron openings in insulative layers for contacts and vias is described. The method uses hardmask formed of carbon enriched titanium nitride. The hardmask has a high selectivity for etching contact and via openings in relatively thick insulative layers. The high selectivity requires a relatively thin hardmask which can be readily patterned by thin photoresist masks, making the process highly desirable for DUV photolithography. The hardmask is formed by MOCVD using a metallorganic titanium precursor. By proper selection of the MOCVD deposition conditions, a controlled amount of carbon is incorporated into the TiN film. The carbon is released as the hardmask erodes during plasma etching and participates in the formation of a protective polymer coating along the sidewalls of the opening being etched in the insulative layer. The protective sidewall polymer inhibits lateral chemical etching and results in openings with smooth, straight, and near-vertical sidewalls without loss of dimensional integrity.
摘要翻译：描述了用于在接触和通孔的绝缘层中蚀刻二分之一微米开口的方法。该方法使用由富碳氮化钛形成的硬掩模。硬掩模在相对较厚的绝缘层中对蚀刻接触和通孔的选择性很高。高选择性需要相对薄的硬掩模，其可以通过薄的光致抗蚀剂掩模容易地图案化，使得该工艺对于DUV光刻非常期望。硬掩模由MOCVD使用金属有机钛前体形成。通过适当选择MOCVD沉积条件，将受控量的碳纳入TiN膜中。在等离子体蚀刻期间，随着硬掩模腐蚀而释放碳，并且参与沿着在绝缘层中蚀刻的开口的侧壁形成保护性聚合物涂层。保护性侧壁聚合物抑制侧向化学蚀刻并导致具有平滑，直的和近垂直的侧壁的开口，而不损失尺寸完整性。

83. 发明授权

US06265317B1 Top corner rounding for shallow trench isolation 有权
标题翻译：用于浅沟槽隔离的顶角圆角
公开(公告)号：US06265317B1
公开(公告)日：2001-07-24
申请号：US09756529
申请日：2001-01-09
申请人： Hsien-Kuang Chiu , Fang-Cheng Chen , Hun-Jan Tao
发明人： Hsien-Kuang Chiu , Fang-Cheng Chen , Hun-Jan Tao
IPC分类号： H01L21302
CPC分类号： H01L21/76232 , H01L21/0335 , H01L21/3065 , H01L21/31116 , H01L21/31612 , H01L21/3185
摘要： A process for top-corner rounding at the rim of shallow trenches of the type used for STI is described. This is achieved by first forming the trench using a silicon nitride hard mask having a layer of pad oxide between itself and the silicon surface. The silicon nitride is then briefly and selectively etched so that it pulls back from over the trench rim and exposes a small amount of the underlying pad oxide. Rounding by means of sputtering is then effected with the pad oxide serving to protect the underlying silicon until just before rounding takes place. The result is smoothly rounded corners free of facets and overhangs.
摘要翻译：描述了用于STI类型的浅沟槽边缘顶角圆角的过程。这通过首先使用在其自身和硅表面之间具有垫氧化物层的氮化硅硬掩模形成沟槽来实现。然后短暂地和选择性地蚀刻氮化硅，使得其从沟槽边缘上方拉回并暴露少量的下面的衬垫氧化物。然后通过溅射进行四舍五入，衬垫氧化物用于保护下面的硅，直到发生四舍五入为止。结果是平滑的圆角没有方面和悬垂。

84. 发明授权

US6025273A Method for etching reliable small contact holes with improved profiles for semiconductor integrated circuits using a carbon doped hard mask 失效
标题翻译：用于使用碳掺杂的硬掩模来蚀刻具有改进的半导体集成电路的轮廓的可靠的小接触孔的方法
公开(公告)号：US6025273A
公开(公告)日：2000-02-15
申请号：US55433
申请日：1998-04-06
申请人： Chao-Cheng Chen , Chia-Shiung Tsai , Hun-Jan Tao
发明人： Chao-Cheng Chen , Chia-Shiung Tsai , Hun-Jan Tao
IPC分类号： H01L21/033 , H01L21/311 , H01L21/768 , H01L23/522 , H01L21/283
CPC分类号： H01L21/31144 , H01L21/76816 , H01L23/5226 , H01L21/0332 , H01L21/31116 , H01L2924/0002
摘要： A method is achieved for fabricating small contact holes in an interlevel dielectric (ILD) layer for integrated circuits. The method increases the ILD etch rate while reducing residue build-up on the contact hole sidewall. This provides a very desirable process for making contact holes small than 0.25 um in width. After depositing the ILD layer over the partially completed integrated circuit which includes patterned doped first polysilicon layers, a second polysilicon layer is deposited and doped with carbon by ion implantation. A photoresist mask is used to etch openings in the carbon doped polysilicon layer to form a hard mask. The photoresist is removed, and the contact holes are plasma etched in the ILD layer while free carbon released from the hard mask, during etching, reduces the free oxygen in the plasma. This results in an enhanced fluorine (F.sup.+) etch rate for the contact holes in the ILD layer and reduces the residue build-up on the sidewalls of the contact holes. The hard mask is anneal in O.sub.2 to form an oxide layer and any surface carbon is removed in a wet etch. Reliable metal plugs can now be formed by depositing a barrier layer, such as titanium (Ti) or titanium nitride (TiN) and a metal such as tungsten (W) and etching back or chemical/mechanical polishing back to the oxide layer.
摘要翻译：实现了用于在用于集成电路的层间电介质（ILD）层中制造小接触孔的方法。该方法增加了ILD蚀刻速率，同时减少了接触孔侧壁上的残留物积聚。这提供了使接触孔宽度小于0.25μm的非常理想的方法。在包括图案化掺杂的第一多晶硅层的部分完成的集成电路上沉积ILD层之后，通过离子注入沉积第二多晶硅层并掺杂碳。光致抗蚀剂掩模用于蚀刻碳掺杂多晶硅层中的开口以形成硬掩模。去除光致抗蚀剂，并且在ILD层中对接触孔进行等离子体蚀刻，而在蚀刻期间从硬掩模释放出的游离碳降低了等离子体中的游离氧。这导致ILD层中的接触孔的氟（F +）蚀刻速率增加，并减少了接触孔的侧壁上的残留物积聚。硬掩模在O 2中退火以形成氧化物层，并且在湿蚀刻中除去任何表面碳。现在可以通过沉积诸如钛（Ti）或氮化钛（TiN）和诸如钨（W）的金属的阻挡层并且将氧化物层回蚀刻或化学/机械抛光来形成可靠的金属插塞。

85. 发明授权

US5981398A Hard mask method for forming chlorine containing plasma etched layer 失效
标题翻译：用于形成含氯等离子体蚀刻层的硬掩模方法
公开(公告)号：US5981398A
公开(公告)日：1999-11-09
申请号：US58122
申请日：1998-04-10
申请人： Chia-Shiung Tsai , Chao-Cheng Chen , Hun-Jan Tao
发明人： Chia-Shiung Tsai , Chao-Cheng Chen , Hun-Jan Tao
IPC分类号： H01L21/3213 , H01L21/3065
CPC分类号： H01L21/32136 , H01L21/32137 , H01L21/32139
摘要： A method for forming a chlorine containing plasma etched patterned layer. There is first provided a substrate 10 employed within a microelectronics fabrication. There is then formed over the substrate a blanket target layer 12 formed of a material susceptible to etching within a second plasma employing a chlorine containing etchant gas composition. There is then formed upon the blanket target a blanket hard mask layer 14 formed of a material selected from the group consisting of silsesquioxane spin-on-glass (SOG) materials and amorphous carbon materials. There is then formed upon the blanket hard mask layer a patterned photoresist layer 16. There is then etched while employing the patterned photoresist layer as a first etch mask layer and while employing a first plasma employing a fluorine containing etchant gas composition the blanket hard mask layer to form a patterned hard mask layer. Finally, there is then etched while employing at least the patterned hard mask layer as a second etch mask layer and while employing the second plasma employing the chlorine containing etchant gas composition the blanket target layer to form the patterned target layer.
摘要翻译：一种形成含氯等离子体蚀刻图案层的方法。首先提供了在微电子制造中使用的衬底10。然后在衬底上形成由使用含氯蚀刻剂气体组合物在第二等离子体内易于蚀刻的材料形成的覆盖层目标层12。然后在橡皮布目标上形成由选自倍半硅氧烷旋涂玻璃（SOG）材料和无定形碳材料的材料形成的橡皮布硬掩模层14。然后在橡皮布硬掩模层上形成图案化的光致抗蚀剂层16.然后在使用图案化的光致抗蚀剂层作为第一蚀刻掩模层的同时进行蚀刻，并且在使用含氟蚀刻剂气体组合物的第一等离子体的同时，以形成图案化的硬掩模层。最后，在使用至少图案化的硬掩模层作为第二蚀刻掩模层的同时蚀刻，并且在使用含氯蚀刻剂气体组合物的第二等离子体时，覆盖目标层以形成图案化目标层。

86. 发明授权

US5925575A Dry etching endpoint procedure to protect against photolithographic misalignments 失效
标题翻译：干蚀刻终点程序以防光刻不对准
公开(公告)号：US5925575A
公开(公告)日：1999-07-20
申请号：US940002
申请日：1997-09-29
申请人： Hun-Jan Tao , Chia-Shiung Tsai
发明人： Hun-Jan Tao , Chia-Shiung Tsai
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/00
CPC分类号： H01L21/31056 , H01L21/76224
摘要： A process for forming a planarized, insulator, or silicon oxide filled shallow trench has been developed. The process features a hybrid planarization procedure, comprised of an initial dry etching cycle, used to remove all but about 100 to 500 Angstroms of silicon oxide, from subsequent device regions, or regions outside the insulator filled trench. Silicon oxide residing on the insulator filled trench is protected by a photoresist shape. A final chemical mechanical polishing procedure is than employed to remove both the silicon oxide, on the insulator filled shallow trench, as well as removing the remaining silicon oxide on silicon nitride, in subsequent device regions. An endpoint monitoring procedure allows the detection of the remaining 100 to 500 Angstroms of silicon oxide, on silicon nitride. This allows the procedure to be terminated at this stage, thus avoiding gouging or trenching phenomena of insulator in the shallow trench, which can occur due to misalignment of the masking photoresist shape to the underlying insulator filled trench.
摘要翻译：已经开发了用于形成平坦化，绝缘体或氧化硅填充的浅沟槽的工艺。该方法具有混合平面化方法，其包括初始干蚀刻循环，用于从后续器件区域或绝缘体填充沟槽外部的区域除去所有但约100至500埃的氧化硅。位于绝缘体填充沟槽上的硅氧化物被光致抗蚀剂形状保护。最后的化学机械抛光方法不仅用于除去在绝缘体填充的浅沟槽上的氧化硅，以及在随后的器件区域中去除氮化硅上剩余的氧化硅。端点监测程序允许在氮化硅上检测剩余的100至500埃的氧化硅。这允许在该阶段终止该过程，从而避免由于掩模光致抗蚀剂形状与下面的绝缘体填充的沟槽的未对准而在浅沟槽中产生的凹陷或挖沟现象。

87. 发明授权

US5904566A Reactive ion etch method for forming vias through nitrogenated silicon oxide layers 失效
标题翻译：用于通过氮化氧化硅层形成通孔的反应离子蚀刻方法
公开(公告)号：US5904566A
公开(公告)日：1999-05-18
申请号：US868842
申请日：1997-06-09
申请人： Hun-Jan Tao , Chia-Shiung Tsai
发明人： Hun-Jan Tao , Chia-Shiung Tsai
IPC分类号： H01L21/311 , H01L21/46
CPC分类号： H01L21/31116
摘要： A method for forming a via through a nitrogenated silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a nitrogenated silicon oxide layer. There is then formed upon the nitrogenated silicon oxide layer a patterned photoresist layer. Finally, there is then etched the nitrogenated silicon oxide layer through a reactive ion etch (RIE) plasma etch method while employing the patterned photoresist layer as a patterned photoresist etch mask layer to form a via through the nitrogenated silicon oxide layer. The reactive ion etch (RIE) method employs an etchant gas composition comprising: (1) a perfluorocarbon having a carbon:fluorine atomic ratio at least about 1:3; (2) oxygen; and (3) argon.
摘要翻译：一种通过氮化氧化硅层形成通孔的方法。首先提供基板。然后在衬底上形成氮化氧化硅层。然后在氮化氧化硅层上形成图案化的光致抗蚀剂层。最后，然后通过反应离子蚀刻（RIE）等离子体蚀刻方法蚀刻氮化氧化硅层，同时使用图案化的光致抗蚀剂层作为图案化的光致抗蚀剂蚀刻掩模层，以形成通过氮化氧化硅层的通孔。反应离子蚀刻（RIE）方法采用蚀刻剂气体组合物，其包括：（1）碳氟原子比至少约1:3的全氟化碳; （2）氧气; 和（3）氩气。

88. 发明授权

US5837599A Wafer surface modification for improved electrostatic chucking efficiency 失效
标题翻译：晶圆表面改性，提高静电吸附效率
公开(公告)号：US5837599A
公开(公告)日：1998-11-17
申请号：US695006
申请日：1996-08-09
申请人： Hun-Jan Tao , Chia-Shiung Tsai
发明人： Hun-Jan Tao , Chia-Shiung Tsai
IPC分类号： H01L21/683 , H01L21/20
CPC分类号： H01L21/6831 , Y10S438/928
摘要： A method of improving electrostatic chucking efficiency between a silicon wafer which has an oxide layer formed on a back side and a susceptor positioned in a wafer processing chamber wherein the back side is opposite to the side of the wafer to be processed for integrated circuit devices including the steps of first forming an electrically conducting layer on top of the oxide layer by transforming to a more hydrophilic oxide structure and then positioning the wafer on the susceptor with the electrically conducting layer contacting the susceptor.
摘要翻译：一种提高在背面形成有氧化层的硅晶片与位于晶片处理室中的基座之间的静电夹持效率的方法，其中背面与用于集成电路器件的待处理晶片侧相反，首先通过转变为更亲水的氧化物结构，然后将晶片定位在基座上，使导电层与基座接触，首先在氧化物层的顶部上形成导电层的步骤。

89. 发明授权

US5348841A Organic dye-in-polymer (DIP) medium for write-once-read-many (WORM) optical discs 失效
标题翻译：用于一次写入（WORM）光盘的有机染料聚合物（DIP）介质
公开(公告)号：US5348841A
公开(公告)日：1994-09-20
申请号：US42754
申请日：1993-04-06
申请人： Hun-Jan Tao , Hwa-Fu Chen
发明人： Hun-Jan Tao , Hwa-Fu Chen
IPC分类号： G11B7/24 , G11B7/244 , G11B7/245 , G11B7/247 , G03C1/72
CPC分类号： G11B7/24 , G11B7/244 , G11B7/245 , G11B7/247 , Y10S430/146
摘要： A dye containing solution composition for use in forming optical recording media comprises about 0.1 to about 5 parts cyanine dye; about 0.1 to about 5 parts polyvinyl acetate resin and about 100 to about 90 parts co-solvents. The dye containing solution is applied to a substrate of an optical recording medium by a spin coating process to form a recording layer having a uniform thickness. The resultant optical recording medium is suitable for reading and writing with a laser beam.
摘要翻译：用于形成光学记录介质的含染料溶液组合物包含约0.1至约5份的花青染料; 约0.1至约5份聚乙酸乙烯酯树脂和约100至约90份共溶剂。通过旋转涂布法将含染料的溶液施加到光记录介质的基板上，形成厚度均匀的记录层。所得的光记录介质适用于用激光束进行读写。

90. 发明授权

US08367563B2 Methods for a gate replacement process 有权
标题翻译：门更换过程的方法
公开(公告)号：US08367563B2
公开(公告)日：2013-02-05
申请号：US12575280
申请日：2009-10-07
申请人： Matt Yeh , Hui Ouyang , Da-Yuan Lee , Kuang Yuan Hsu , Hun-Jan Tao , Xiong-Fei Yu
发明人： Matt Yeh , Hui Ouyang , Da-Yuan Lee , Kuang Yuan Hsu , Hun-Jan Tao , Xiong-Fei Yu
IPC分类号： H01L21/3205
CPC分类号： H01L29/401 , H01L21/823828 , H01L21/823835 , H01L21/823842 , H01L29/66545
摘要： A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process.
摘要翻译：公开了一种制造半导体器件的方法。在一个实施例中，该方法可以包括提供衬底; 在所述衬底上形成包括第一虚拟栅极的栅极结构; 从栅极结构去除第一伪栅极以形成沟槽; 形成界面层，高k电介质层和覆盖层以部分地填充在沟槽中; 在所述覆盖层上形成第二虚拟栅极，其中所述第二伪栅极填充所述沟槽; 并用金属栅极替换第二虚拟栅极。在一个实施例中，该方法可以包括提供衬底; 在衬底上形成界面层; 在界面层上形成高k电介质层; 在所述高k电介质层上形成蚀刻停止层; 在所述蚀刻停止层上形成包括低热预算硅的覆盖层; 在覆盖层上形成虚拟栅极层; 形成栅极结构; 并进行门更换处理。

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