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81. 发明授权

US08850379B2 Method of and system for generating optimized semiconductor component layout 有权
标题翻译：用于生成优化的半导体元件布局的方法和系统
公开(公告)号：US08850379B2
公开(公告)日：2014-09-30
申请号：US13352738
申请日：2012-01-18
申请人： Chien-Hung Chen , Yung-Chow Peng , Chung-Hui Chen , Chih Ming Yang
发明人： Chien-Hung Chen , Yung-Chow Peng , Chung-Hui Chen , Chih Ming Yang
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F2217/02 , G06F2217/06 , G06F2217/08 , G06F2217/12 , H01L27/0207 , H01L29/94
摘要： A method of generating an optimized layout of semiconductor components in conformance with a set of design rules includes generating, for a unit cell including one or more semiconductor components, a plurality of configurations each of which satisfies some, but not all, of the design rules. For each configuration, it is checked whether a layout, which is a repeating pattern of the unit cell, satisfies the remaining design rules. Among the configurations which satisfy all of the design rules, the configuration providing an optimal value of a property is selected for generating the optimized layout of the semiconductor components.
摘要翻译：根据一组设计规则生成半导体部件的优化布局的方法包括为包括一个或多个半导体部件的单元单元生成多个配置，每个配置满足设计规则的一些但不是全部。对于每个配置，检查作为单位单元的重复图案的布局是否满足剩余的设计规则。在满足所有设计规则的配置中，选择提供最佳的属性值的配置用于生成半导体部件的优化布局。

82. 发明授权

US08736355B2 Device layout for reference and sensor circuits 有权
标题翻译：参考和传感器电路的器件布局
公开(公告)号：US08736355B2
公开(公告)日：2014-05-27
申请号：US13494060
申请日：2012-06-12
申请人： Jaw-Juinn Horng , Chung-Hui Chen , Sun-Jay Chang , Chia-Hsin Hu
发明人： Jaw-Juinn Horng , Chung-Hui Chen , Sun-Jay Chang , Chia-Hsin Hu
IPC分类号： G05F1/10
CPC分类号： H01L27/0814 , H01L27/0207
摘要： A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction.
摘要翻译：带隙参考电路包括耦合在第一电源节点和一对中间电压节点之间的基于误差放大器的电流镜，以及用于提供比例绝对温度（PTAT）电流的匹配二极管对。匹配二极管对包括连接在来自一对中间电压节点的第一中间电压节点和第二电源节点之间的第一二极管，以及与来自所述一对中间电压的第二中间电压节点之间的电阻器串联连接的第二二极管节点和第二个供应节点。每个二极管具有一个同相结合的P-N二极管结。

83. 发明授权

US08692306B2 Decoupling capacitor and method of making same 有权
标题翻译：去耦电容及其制作方法
公开(公告)号：US08692306B2
公开(公告)日：2014-04-08
申请号：US13344137
申请日：2012-01-05
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L27/067 , H01L21/76224 , H01L23/5223 , H01L23/5286 , H01L27/0207 , H01L27/0629 , H01L27/0635 , H01L28/40 , H01L28/88 , H01L29/0649 , H01L29/66477 , H01L29/73 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns.
摘要翻译：半导体衬底具有至少两个有源区，每个有源区具有至少一个有源器件，其包括栅极电极层和有源区之间的浅沟槽隔离（STI）区域。去耦电容器包括在STI区域上形成在同一栅极电极层中的第一和第二虚设导电图案。第一和第二虚拟导电区域未连接到至少一个有源器件中的任何一个。第一虚拟导电图案连接到第一电位的源。第二虚拟导电图案连接到第二电位的源。介电材料设置在第一和第二虚设导电图案之间。

84. 发明授权

US08546953B2 Through silicon via (TSV) isolation structures for noise reduction in 3D integrated circuit 有权
标题翻译：通过硅通孔（TSV）隔离结构降低3D集成电路
公开(公告)号：US08546953B2
公开(公告)日：2013-10-01
申请号：US13324405
申请日：2011-12-13
申请人： Jaw-Juinn Horng , Chia-Lin Yu , Chung-Hui Chen , Der-Chyang Yeh , Yung-Chow Peng
发明人： Jaw-Juinn Horng , Chia-Lin Yu , Chung-Hui Chen , Der-Chyang Yeh , Yung-Chow Peng
IPC分类号： H01L23/48 , H01L29/40 , H01L23/04 , H01L21/44
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.
摘要翻译：提供通过硅通孔（TSV）隔离结构，并且抑制诸如在由3D集成电路封装中使用的携带有源TSV的信号引起的时候可能传播通过半导体衬底的电噪声。隔离TSV结构被氧化物衬垫和周围的掺杂剂杂质区包围。周围的掺杂剂杂质区域可以是耦合到接地的P型掺杂剂杂质区域或者可以有利地连接到VDD的N型掺杂剂杂质区域。 TSV隔离结构有利地设置在有源信号承载TSV和有源半导体器件之间，并且TSV隔离结构可以形成为将有源信号传输TSV结构与有源半导体器件隔离的阵列。

85. 发明申请

US20120104569A1 INTEGRATED CIRCUITS AND FABRICATION METHODS THEREOF 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US20120104569A1
公开(公告)日：2012-05-03
申请号：US13025763
申请日：2011-02-11
申请人： Chung-Hui CHEN
发明人： Chung-Hui CHEN
IPC分类号： H01L23/552 , H01L21/768
CPC分类号： H01L23/552 , H01L23/5225 , H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a signal line routed in a first direction. A first shielding pattern is disposed substantially parallel with the signal line. The first shielding pattern has a first edge having a first dimension and a second edge having a second dimension. The first edge is substantially parallel with the signal line. The first dimension is larger than the second dimension. A second shielding pattern is disposed substantially parallel with the signal line. The second shielding pattern has a third edge having a third dimension and a fourth edge having a fourth dimension. The third edge is substantially parallel with the signal line. The third dimension is larger than the fourth dimension. The fourth edge faces the second edge. A first space is between the second and fourth edges.
摘要翻译：集成电路包括沿第一方向布线的信号线。第一屏蔽图案基本上与信号线平行设置。第一屏蔽图案具有具有第一尺寸的第一边缘和具有第二尺寸的第二边缘。第一边缘基本上与信号线平行。第一个维度大于第二个维度。第二屏蔽图案基本上与信号线平行设置。第二屏蔽图案具有具有第三尺寸的第三边缘和具有第四尺寸的第四边缘。第三边缘基本上与信号线平行。第三维度大于第四维度。第四个边缘面向第二个边缘。第一空间在第二和第四边之间。

86. 发明申请

US20070038813A1 SYSTEM AND METHOD FOR CACHE COHERENCE 失效
标题翻译：高速缓存的系统和方法
公开(公告)号：US20070038813A1
公开(公告)日：2007-02-15
申请号：US11161616
申请日：2005-08-10
申请人： Hong-Men Su , Yung-Chung Liu , Chih-Yung Chiu , Chung-Hui Chen
发明人： Hong-Men Su , Yung-Chung Liu , Chih-Yung Chiu , Chung-Hui Chen
IPC分类号： G06F13/28
CPC分类号： G06F12/0817
摘要： A system and a method for cache coherence are provided. The system includes a memory apparatus, a detector, a plurality of access-consumers and a plurality of pass-gates. At least one of the access-consumers is a processor having a cache. When the processor replaces the first data in cache with the second data read from the memory apparatus, the process issues the read second data request first, followed by the write-back first data request. The detector provides a detecting signal when the processor issues the read second data request and cancels the provided detecting signal when the processor issues the write-back first data request. Each pass-gate decides whether to pass the third access request outputting from each corresponding access-consumer and transmit it to the memory apparatus according to the detecting signal respectively.
摘要翻译：提供了一种用于高速缓存一致性的系统和方法。该系统包括存储装置，检测器，多个访问消费者和多个传递门。访问消费者中的至少一个是具有高速缓存的处理器。当处理器使用从存储器装置读取的第二数据替换高速缓存中的第一数据时，该处理首先发出读取的第二数据请求，随后是回写第一数据请求。当处理器发出读取的第二数据请求时，检测器提供检测信号，并在处理器发出回写第一数据请求时取消所提供的检测信号。每个通过门决定是否通过从每个对应的访问消费者输出的第三访问请求，并且分别根据检测信号将其发送到存储装置。

87. 发明授权

US07119600B2 Wide common mode high-speed differential receiver using thin and thick gate oxide MOSFETS in deep-submicron technology 有权
标题翻译：宽泛型高速差分接收器采用薄型和厚栅氧化物MOSFETS在深亚微米技术中
公开(公告)号：US07119600B2
公开(公告)日：2006-10-10
申请号：US10827958
申请日：2004-04-20
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： H03K5/22
CPC分类号： H04L25/0292 , H03K19/018528 , H04L25/0272
摘要： A high speed receiver circuit is disclosed with a high supply voltage and operable with other circuits operating at a low supply voltage. The receiver circuit comprises first and second differential input signals controlling first and second current switches. It also includes a top current supply connected to the high supply voltage for providing a current to be passed either through the first current switch and a first bottom current supply or the second current switch and a second bottom current supply. Further included are first and second resistors connected to the low supply voltage and in a series with the first or second bottom current supplies respectively. First and second differential output signals are produced at a point between each pair of the resistors and the bottom current supply. A common mode voltage of the first and second differential output signals is lower than the low supply voltage.
摘要翻译：公开了一种具有高电源电压的高速接收器电路，并且可以与其他以低电源电压工作的电路一起使用。接收器电路包括控制第一和第二电流开关的第一和第二差分输入信号。它还包括连接到高电源电压的顶部电流源，以提供通过第一电流开关和第一底部电流源或第二电流开关和第二底部电流源的电流。还包括分别连接到低电源电压并与第一或第二底部电流源串联的第一和第二电阻器。在每对电阻器和底部电流源之间的点处产生第一和第二差分输出信号。第一和第二差分输出信号的共模电压低于低电源电压。

88. 发明申请

US20060022739A1 High speed digital level shifter 有权
标题翻译：高速数字电平转换器
公开(公告)号：US20060022739A1
公开(公告)日：2006-02-02
申请号：US10901700
申请日：2004-07-28
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： H03L5/00
CPC分类号： H03K17/102 , H03K3/356113 , H03K17/063
摘要： A high-speed digital level shifter is described. The preferred embodiment shifts an input signal with a lower amplitude to a signal with a higher amplitude. The level shifter includes a signal driver circuit to drive up the input signal to a driver signal having higher voltages. The driver signal is used to drive an output circuit that generates an output signal having amplitude of a high voltage power source. The output circuit has improved performance being driven by the driver input signal. A signal stepper is added to further improve the performance by pulling up the output voltage in two stages.
摘要翻译：描述高速数字电平转换器。优选实施例将具有较低振幅的输入信号移位到具有较高振幅的信号。电平移位器包括用于将输入信号升高到具有较高电压的驱动器信号的信号驱动器电路。驱动器信号用于驱动产生具有高电压电源幅度的输出信号的输出电路。输出电路具有由驱动器输入信号驱动的改进的性能。添加信号步进器以通过分两级提升输出电压来进一步提高性能。

89. 发明申请

US20050225420A1 Deep submicron CMOS compatible suspending inductor 有权
标题翻译：深亚微米CMOS兼容的悬挂电感
公开(公告)号：US20050225420A1
公开(公告)日：2005-10-13
申请号：US10820396
申请日：2004-04-08
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： H01F5/00 , H01F17/00 , H01F17/02 , H01F41/04 , H01L23/522 , H01L27/08
CPC分类号： H01F17/02 , H01F17/0006 , H01F41/041 , H01L23/5227 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： A new method is provided for the creation of an inductor. Layers of pad oxide, a thick layer of dielectric and an etch stop layer are successively created over the surface of a substrate. The layers of etch stop material and dielectric are patterned and etched, creating an inductor pattern whereby the inductor pattern created in the layer of dielectric is located close to the surface of the layer of dielectric. Optionally, support pillars for the inductor can be created at this time through the layer of dielectric. The inductor pattern in the layer of dielectric is filled with metal, the etch stop layer and the layer of dielectric is removed from above the metal fill, additionally exposing the layer of dielectric. The additionally exposed layer of dielectric is etched using a slope etcher. Since the layer of dielectric is preferably an oxide based layer of dielectric, this exposure will significantly remove the layer of dielectric, creating an air gap surrounding the inductor without affecting the optionally created support pillars or the created inductor.
摘要翻译：提供了一种创建电感器的新方法。在衬底的表面上连续地形成衬垫氧化物层，电介质层和蚀刻停止层。蚀刻停止材料和电介质的层被图案化和蚀刻，产生电感器图案，由此在电介质层中产生的电感器图案位于电介质层的表面附近。可选地，可以在此时通过电介质层产生用于电感器的支撑柱。电介质层中的电感器图案用金属填充，蚀刻停止层和电介质层从金属填充物上方移除，另外暴露电介质层。使用斜率蚀刻器蚀刻另外暴露的电介质层。由于电介质层优选是基于氧化物的电介质层，因此该曝光将显着地去除电介质层，从而在不影响可选地产生的支撑柱或所产生的电感器的情况下产生围绕电感器的气隙。

90. 发明申请

US20050206362A1 Low-voltage bandgap reference circuit 有权
标题翻译：低压带隙基准电路
公开(公告)号：US20050206362A1
公开(公告)日：2005-09-22
申请号：US10804708
申请日：2004-03-19
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： G05F3/16 , G05F3/30 , H03M1/06
CPC分类号： G05F3/30 , Y10S323/907
摘要： A system and method is disclosed for providing a bandgap reference voltage generator that can successfully operate with a low operating voltage. Three current sources are controlled to provide same amount of current through three paths. The first current source is used to enable a first negative temperature coefficient module, while the second and third current sources are used to enable a first positive temperature coefficient module. The three current sources together are used to enable a reference voltage output module, which is connected to a current summing module for producing a bandgap reference voltage independent of temperature variations.
摘要翻译：公开了一种用于提供能够以低工作电压成功操作的带隙参考电压发生器的系统和方法。控制三个电流源以通过三条路径提供相同量的电流。第一电流源用于启用第一负温度系数模块，而第二和第三电流源用于启用第一正温度系数模块。三个电流源一起用于启用参考电压输出模块，其连接到电流求和模块，用于产生与温度变化无关的带隙基准电压。

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