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81. 发明授权

US5852568A System and method for a fast carry/sum select adder 失效
标题翻译：用于快速进位/和选择加法器的系统和方法
公开(公告)号：US5852568A
公开(公告)日：1998-12-22
申请号：US788391
申请日：1997-01-27
申请人： Nalini Ranjan
发明人： Nalini Ranjan
IPC分类号： G06F7/507 , G06F7/50 , G06F7/506 , G06F7/508
CPC分类号： G06F7/507
摘要： An adder system includes at least one adder block subsystem. Each adder block subsystem includes a pair of input signal lines, an adder circuit block having a conditional sum-select and a conditional carry-select, a sum-high line, a sum-low line, a carry-high line, carry-low line, a sum selection switch, a carry selection switch, a carry forward line, and an output signal line. The input lines are individual bit lines that are paired together from the least significant bit to the most significant bit. Within the adder circuit block, pairs of the input bit lines are coupled to the conditional sum-select and the conditional carry-select. The conditional sum-select is coupled to the sum-high and sum-low lines and the conditional carry-select is coupled to the carry-high and carry-low line. The sum selection switch selectively couples the output signal line to the sum-high or the sum-low line. The carry selection switch selectively couples the carry-high or carry-low line to the carry forward line that is coupled to the next adder subsystem which is structured similarly. The carry signal of the adder system is determined through the conditional carry selects of the adder circuit blocks. Each conditional carry-select includes logic OR and logic AND subcircuits to which each of the pairs of input bit lines is respectively coupled. The outputs of the logic OR and logic AND subcircuits are coupled to one or more line multiplexes to selectively produce a logic high or logic low signal that serves as the individual carry bit signals for the carry signal. A method for an adder system is also disclosed.
摘要翻译：加法器系统包括至少一个加法器块子系统。每个加法器块子系统包括一对输入信号线，具有条件和选择和条件进位选择的加法器电路块，和和线，和和线，进位高线，进位电位线，和选择开关，进位选择开关，进位线和输出信号线。输入线是从最低有效位到最高有效位配对的单独位线。在加法器电路块内，输入位线对耦合到条件求和和条件进位选择。条件求和选择被耦合到和高和和线，并且条件进位选择被耦合到进位高和进位低的线。总和选择开关将输出信号线选择性地耦合到和高或低和线。进位选择开关选择性地将进位高或进位低的线耦合到耦合到类似地被构造的下一个加法器子系统的进位线。加法器系统的进位信号通过加法器电路块的条件进位选择来确定。每个条件进位选择包括分别耦合输入位线对中的每一对的逻辑OR和逻辑与子电路。逻辑和逻辑与子电路的输出耦合到一个或多个线路多路复用，以选择性地产生用作进位信号的各个进位位信号的逻辑高或逻辑低电平信号。还公开了一种加法器系统的方法。

82. 发明授权

US5818967A Video decoder engine 失效
标题翻译：视频解码引擎
公开(公告)号：US5818967A
公开(公告)日：1998-10-06
申请号：US490322
申请日：1995-06-12
申请人： Soma Bhattacharjee , Charles C. Stearns
发明人： Soma Bhattacharjee , Charles C. Stearns
IPC分类号： G06T9/00 , H04N7/26 , H04N7/50 , H04N21/2368 , H04N21/434 , H04N21/443 , G06K9/00 , G06K9/36 , G06K9/46 , G06K9/54
CPC分类号： H04N19/42 , H04N19/61 , H04N21/4143 , H04N21/426 , H04N21/42607
摘要： MPEG compressed video data is decompressed in a computer system by sharing computational decompression tasks between the computer system host microprocessor, the graphics accelerator, and a dedicated MPEG processor (video decoder engine) in order to make best use of resources in the computer system. Thus the dedicated MPEG processor is of minimum capability and hence advantageously minimum cost. The host microprocessor is used to decompress the MPEG upper data layers. The more powerful the host microprocessor, the more upper data layers it decompresses. The remainder of the decompression (lower data layers) is performed by the MPEG dedicated processor and/or the graphics accelerator. The video decoder engine is a fast hardwired processor. It has a graceful degradation capability to allow dropping of occasional video frames without displaying any part of a dropped video frame. The video decoder engine has a three stage pipeline structure to minimize circuitry and speed up operation.
摘要翻译：在计算机系统中通过在计算机系统主机微处理器，图形加速器和专用MPEG处理器（视频解码器引擎）之间共享计算解压缩任务来解压缩MPEG压缩视频数据，以便最好地利用计算机系统中的资源。因此，专用MPEG处理器具有最小的能力，因此有利地是最小的成本。主机微处理器用于解压缩MPEG数据层。主机微处理器越强大，其解压缩的数据层越多。解压缩的其余部分（较低数据层）由MPEG专用处理器和/或图形加速器执行。视频解码器引擎是一种快速硬连线处理器。它具有优雅的降级能力，允许偶尔的视频帧丢弃，而不会显示丢弃的视频帧的任何部分。视频解码器引擎具有三级流水线结构，以最小化电路并加速操作。

83. 发明授权

US5778096A Decompression of MPEG compressed data in a computer system 失效
标题翻译：在计算机系统中压缩MPEG压缩数据
公开(公告)号：US5778096A
公开(公告)日：1998-07-07
申请号：US489488
申请日：1995-06-12
申请人： Charles C. Stearns
发明人： Charles C. Stearns
IPC分类号： G06T9/00 , H04N7/26 , H04N7/50 , G06K9/36 , G06K9/46
CPC分类号： H04N21/4143 , H04N19/42 , H04N19/428 , H04N19/436 , H04N19/439 , H04N19/61 , H04N19/90
摘要： MPEG compressed data is decompressed in a computer system by sharing computational decompression tasks between the computer system host microprocessor, the graphics accelerator, and a dedicated MPEG processor in order to make best use of resources in the computer system. Thus the dedicated MPEG processor is of minimum capability and hence advantageously minimum cost. The host microprocessor is used to decompress the MPEG upper data layers. The more powerful the host microprocessor, the more upper data layers it decompresses. The remainder of the decompression (lower data layers) is performed by the MPEG dedicated processor and/or the graphics accelerator.
摘要翻译：在计算机系统中通过在计算机系统主机微处理器，图形加速器和专用MPEG处理器之间共享计算解压缩任务来解压缩MPEG压缩数据，以便最好地利用计算机系统中的资源。因此，专用MPEG处理器具有最小的能力，因此有利地是最小的成本。主机微处理器用于解压缩MPEG数据层。主机微处理器越强大，其解压缩的数据层越多。解压缩的其余部分（较低数据层）由MPEG专用处理器和/或图形加速器执行。

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