专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US07237157B2 Procedure and device for identifying an operating mode of a controlled device 有权
标题翻译：用于识别受控设备的操作模式的过程和设备
公开(公告)号：US07237157B2
公开(公告)日：2007-06-26
申请号：US10844978
申请日：2004-05-13
申请人： David Naura , Bertrand Bertrand , Mohamad Chehadi
发明人： David Naura , Bertrand Bertrand , Mohamad Chehadi
IPC分类号： G11C29/08 , G11C29/06
CPC分类号： G11C29/46
摘要： A procedure is provided for identifying an operating mode of a device, such as an EEPROM memory that communicates according to a communication protocol, such as “I2C” (Inter Integrated Circuit). The signal is an “ACK” or “ACKNOWLEDGE” signal. At least one operating mode of a device is identified by a time lag from the time the signal (ACK) is transmitted relative to the time foreseen by the protocol for the signal. This approach can be used to verify that the test mode commands (read or write) have been taken into account correctly.
摘要翻译：提供了用于识别诸如“I 2 C”（集成内部电路）等通信协议进行通信的EEPROM存储器的装置的操作模式的过程。信号是“ACK”或“ACKNOWLEDGE”信号。从信号（ACK）相对于信号协议所预见的时间发送的时间，通过时间滞后来识别设备的至少一个操作模式。该方法可用于验证测试模式命令（读取或写入）是否被正确地考虑在内。

72. 发明授权

US07075838B2 Semiconductor device and test method of testing the same 失效
标题翻译：半导体器件及其测试方法相同
公开(公告)号：US07075838B2
公开(公告)日：2006-07-11
申请号：US10756715
申请日：2004-01-13
申请人： Seong-ho Jeung , Jong-hoon Jung
发明人： Seong-ho Jeung , Jong-hoon Jung
IPC分类号： G11C29/06 , G11C29/50 , G11C11/413 , G11C8/08
CPC分类号： G11C29/12 , G11C11/41 , G11C2029/1202 , G11C2029/1802
摘要： A semiconductor device and a method of testing the semiconductor device are provided. The semiconductor device includes a memory cell array, a sense amplifier, a control circuit, a row decoder, a bitline-pair voltage setting circuit, and a wordline driver. The memory cell array is connected to one of a plurality of wordlines and a plurality of bitline pairs. The memory cell array comprises a plurality of memory cells, wherein each memory cell is connected to one of the plurality of wordlines and the plurality of bitline pairs. The sense amplifier amplifies data read from the memory cell array. The control circuit controls writing/reading of data to/from the memory cell array. The row decoder decodes an address signal and outputs a decoded signal to select one of the plurality of wordlines. The bitline-pair voltage setting circuit sets the voltage of at least one of the plurality of bitline pairs to a bitline test voltage in a test mode. The wordline driver sets the low-level voltages of the plurality of wordlines to a wordline test voltage in the test mode. The wordline test voltage level can be set to be different from the low-level voltage of the plurality of wordlines in a normal operation mode.
摘要翻译：提供半导体器件和测试半导体器件的方法。半导体器件包括存储单元阵列，读出放大器，控制电路，行解码器，位线对电压设置电路和字线驱动器。存储单元阵列连接到多个字线和多个位线对之一。存储单元阵列包括多个存储器单元，其中每个存储器单元连接到多个字线和多个位线对之一。读出放大器放大从存储单元阵列读出的数据。控制电路控制向/从存储单元阵列写入/读取数据。行解码器解码地址信号并输出解码信号以选择多个字线中的一个。位线对电压设定电路在测试模式中将多个位线对中的至少一个的电压设置为位线测试电压。字线驱动器将测试模式中的多个字线的低电平电压设置为字线测试电压。字线测试电压电平可以被设置为与正常操作模式中的多个字线的低电平电压不同。

73. 发明申请

US20050278592A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20050278592A1
公开(公告)日：2005-12-15
申请号：US11002894
申请日：2004-12-03
申请人： Shinichi Yamada , Waichiro Fujieda , Shinichiroh Ikemasu
发明人： Shinichi Yamada , Waichiro Fujieda , Shinichiroh Ikemasu
IPC分类号： G01R31/28 , G11C5/00 , G11C7/02 , G11C7/14 , G11C11/401 , G11C11/4099 , G11C29/00 , G11C29/06 , G11C29/24
CPC分类号： G11C7/14 , G11C11/401 , G11C11/4099 , G11C29/24 , G11C29/50 , G11C2029/5006
摘要： First dummy memory cells connected to a first dummy signal line have the same shape and characteristics as those of a real memory cell. The first dummy memory cells are arranged to be adjacent to outermost real memory cells. A voltage setting circuit changes the voltage of the first dummy signal line from a first voltage to a second voltage in order to write test data onto the first dummy memory cell during a test mode. By writing data of a logic opposite to that of the test data onto the real memory cell adjacent to the first dummy memory cell by means of an operation control circuit, a leak failure that may occur between the first dummy memory cell and the real memory cell adjacent thereto can be checked.
摘要翻译：连接到第一虚拟信号线的第一虚拟存储器单元具有与实际存储单元相同的形状和特性。第一虚拟存储器单元布置成与最外面的真实存储单元相邻。电压设定电路将第一虚拟信号线的电压从第一电压改变为第二电压，以便在测试模式期间将测试数据写入第一虚拟存储器单元。通过使用操作控制电路将与测试数据的逻辑相反的逻辑的数据写入与第一虚拟存储单元相邻的实际存储单元上，可能发生在第一虚拟存储单元和实际存储单元之间的泄漏故障可以检查相邻的位置。

74. 发明申请

US20050218922A1 Method and apparatus for testing defective portion of semiconductor device 有权
标题翻译：用于测试半导体器件的缺陷部分的方法和装置
公开(公告)号：US20050218922A1
公开(公告)日：2005-10-06
申请号：US11088833
申请日：2005-03-25
申请人： Junichi Suzuki , Kohji Kanamori
发明人： Junichi Suzuki , Kohji Kanamori
IPC分类号： G01R31/28 , G01R31/26 , G11C16/06 , G11C29/00 , G11C29/06 , H01L21/66 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G01R31/2621
摘要： An apparatus for testing a defect, includes a semiconductor element. In the semiconductor element, a conductive film is formed on an STI (shallow trench isolation) insulating film, which fills a shallow trench extending into a semiconductor region, through an insulating film in an ordinary state, and the shallow trench is not completely or sufficiently filled with the STI insulating film in a defective state. Also, the apparatus includes a control circuit configured to set a test mode in response to a test mode designation signal, a first voltage applying circuit configured to output a first voltage to the conductive film in the test mode, and a second voltage applying circuit configured to output a second voltage to the semiconductor region in the test mode. The first voltage is higher than the second voltage, and a voltage difference between the first voltage and the second voltage is sufficient to cause breakdown between the conductive film and the semiconductor region in the defective state.
摘要翻译：用于测试缺陷的装置包括半导体元件。在半导体元件中，在通常通过绝缘膜的STI（浅沟槽隔离）绝缘膜上形成导电膜，其通过绝缘膜填充延伸到半导体区域中的浅沟槽，并且浅沟槽不完全或充分填充有缺陷状态的STI绝缘膜。此外，该装置包括：控制电路，被配置为响应于测试模式指定信号设置测试模式;第一电压施加电路，被配置为在测试模式下向导电膜输出第一电压;以及第二电压施加电路，以在测试模式中向半导体区域输出第二电压。第一电压高于第二电压，并且第一电压和第二电压之间的电压差足以导致在缺陷状态下导电膜和半导体区域之间的击穿。

75. 发明授权

US06930938B2 Semiconductor memory device having test mode 失效
标题翻译：具有测试模式的半导体存储器件
公开(公告)号：US06930938B2
公开(公告)日：2005-08-16
申请号：US10442974
申请日：2003-05-22
申请人： Kenichi Yasuda
发明人： Kenichi Yasuda
IPC分类号： G01R31/30 , G01R31/28 , G11C11/401 , G11C29/02 , G11C29/06 , G11C29/00
CPC分类号： G11C29/025 , G11C29/02 , G11C29/12005 , G11C2029/1204
摘要： In a burn-in test, a sense amplifier circuit is separated from each bit line by a bit line separation switch. In this state, a bit line switch circuit connects one of complementary bit lines to a first voltage node, and connects the other complementary bit line to a second voltage node in blocks on both sides. A first bit line voltage supplied by the first voltage node and a second bit line voltage supplied by the second voltage node can be set independently of each other at least in the burn-in test.
摘要翻译：在老化测试中，读出放大器电路通过位线分离开关与每个位线分离。在该状态下，位线开关电路将互补位线之一连接到第一电压节点，并且将另一个互补位线连接到两侧的块中的第二电压节点。至少在老化测试中，由第一电压节点提供的第一位线电压和由第二电压节点提供的第二位线电压可彼此独立设定。

76. 发明授权

US06888766B2 Semiconductor memory device provided with test memory cell unit 失效
标题翻译：具有测试存储单元的半导体存储器件
公开(公告)号：US06888766B2
公开(公告)日：2005-05-03
申请号：US10254647
申请日：2002-09-26
申请人： Kazuhiko Takahashi
发明人： Kazuhiko Takahashi
IPC分类号： G11C11/22 , G11C29/06 , G11C29/50 , H01L21/8246 , H01L27/105 , G11C7/24 , G11C5/02 , G11C29/00
CPC分类号： G11C29/50012 , G11C11/22 , G11C29/24 , G11C29/50 , G11C29/50016
摘要： A semiconductor memory device includes a memory cell block composed of a memory cell unit having memory cells each containing a ferroelectric capacitor, and a test memory cell unit having test memory cells. The layout pattern of the test memory cells is identical to the layout pattern of the memory cells. The test memory cell unit is arranged close to a memory cell of a plurality of memory cells which is at a position where the ferroelectric capacitor is susceptible to degradation. The memory cell unit and test memory cell unit are subjected to a first cycling test consisting of N1 cycles. Then, the test memory cell unit is subjected to a second cycling test consisting of N2 cycles. The sum (N1+N2) of the number of cycles in the first and second cycling tests equals an assurance number of cycles T, where N1
摘要翻译：半导体存储器件包括由具有各自含有铁电电容器的存储单元的存储单元单元和具有测试存储单元的测试存储单元组成的存储单元块。测试存储单元的布局模式与存储器单元的布局模式相同。测试存储单元单元布置在靠近强电介质电容器容易劣化的位置的多个存储单元的存储单元附近。对存储单元单元和测试存储单元单元进行由N 1个循环组成的第一循环测试。然后，对测试存储单元单元进行由N 2个循环组成的第二循环测试。第一循环和第二次循环试验中的循环次数的总和（N N 1 N N N N N 2 N）等于循环T的保证数，其中N 1 < / SUB> 。

77. 发明授权

US06885235B2 Semiconductor integrated circuit device with internal power supply potential generation circuit 失效
标题翻译：具有内部电源电位生成电路的半导体集成电路器件
公开(公告)号：US06885235B2
公开(公告)日：2005-04-26
申请号：US10095080
申请日：2002-03-12
申请人： Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Hiroaki Tanizaki , Tsukasa Ooishi
发明人： Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Hiroaki Tanizaki , Tsukasa Ooishi
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C29/06 , G05F3/04
CPC分类号： G11C5/147
摘要： An internal power supply potential generation circuit includes an overcharge prevention circuit connected to an internal power supply node. The overcharge prevention circuit includes a circuit outputting a signal to be determined that is determined by an internal power supply potential, a differential amplification circuit amplifying a difference in potential between the signal to be determined and a reference potential for output to a node as a signal indicating that current should be drawn, and a current draw circuit drawing current from the internal power supply node in response to the signal indicating that current should be drawn. Thus the semiconductor integrated circuit device of interest can provide a steady internal power supply potential.
摘要翻译：内部电源电位产生电路包括连接到内部电源节点的过充电防止电路。过充电防止电路包括输出由内部电源电位确定的待确定信号的电路，放大要确定的信号之间的电位差和作为输出到节点的参考电位的差分放大电路作为信号表示应该绘制电流，并且响应于指示应当绘制电流的信号，从内部电源节点抽出电流的电流绘制电路。因此，感兴趣的半导体集成电路器件可以提供稳定的内部电源电位。

78. 发明授权

US06839293B2 Word-line deficiency detection method for semiconductor memory device 失效
标题翻译：半导体存储器件的字线缺陷检测方法
公开(公告)号：US06839293B2
公开(公告)日：2005-01-04
申请号：US10288461
申请日：2002-11-06
申请人： Satoru Kawamoto , Motoki Mizutani , Shinji Nagai , Yoshiharu Kato
发明人： Satoru Kawamoto , Motoki Mizutani , Shinji Nagai , Yoshiharu Kato
IPC分类号： G01R31/26 , G01R31/28 , G11C11/401 , G11C29/02 , G11C29/04 , G11C29/06 , G11C29/50 , G11C29/00 , G11C7/00
CPC分类号： G11C29/025 , G11C17/14 , G11C29/02 , G11C29/50 , G11C2029/0403
摘要： A semiconductor memory device having a burn-in test capability. The semiconductor memory device includes a detection circuit, which is connected to the plurality of word lines. The detection circuit detects whether a stress voltage for a burn-in test has been applied to all of the word lines along their entire lengths in the burn-in test.
摘要翻译：具有老化测试能力的半导体存储器件。半导体存储器件包括连接到多个字线的检测电路。检测电路检测在老化测试中，老化测试的应力电压是否已沿其整个长度应用于所有字线。

79. 发明授权

US6160745A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US6160745A
公开(公告)日：2000-12-12
申请号：US515833
申请日：2000-02-29
申请人： Hiroaki Hashimoto
发明人： Hiroaki Hashimoto
IPC分类号： G11C29/04 , G11C29/00 , G11C29/06 , G11C29/50
CPC分类号： G11C29/78 , G11C29/50
摘要： A semiconductor storage device contains a row redundancy cell array in which redundancy cells are arranged in connection with redundancy word lines respectively and a memory cell array in which memory cells are arranged in connection with word lines respectively. In a normal operation mode, the word lines are sequentially activated in response to input addresses, so that stored information is read out from each of the memory cells of the memory cell array. If an input address coincides with a defective word line address designating a word line being connected with a defective memory cell within the memory cell array, a redundancy word line is selectively activated as a replacement of the word line which is inhibited from being activated, so that stored information is read out from each of the redundancy cells connected with the redundancy word line. In a burn-in test mode, the redundancy word lines and word lines are collectively activated and are subjected to stress, so that a burn-in test is performed on the redundancy cells and memory cells collectively. Thus, it is possible to reduce the time required for the burn-in test in manufacture. In a defectiveness test mode, the redundancy word lines are sequentially activated and are subjected to stress, so that a defectiveness test is performed to check each of the redundancy cells in quality.
摘要翻译：半导体存储装置包括行冗余单元阵列，其中冗余单元分别与冗余字线连接布置，存储单元阵列分别与字线连接地存储存储单元。在正常操作模式中，字线响应于输入地址被依次激活，从而从存储单元阵列的每个存储单元读出存储的信息。如果输入地址与指定与存储单元阵列内的有缺陷的存储单元连接的字线的缺陷字线地址一致，则冗余字线被选择性地激活为禁止被激活的字线的替换，因此从与冗余字线连接的每个冗余单元中读出存储的信息。在老化测试模式中，冗余字线和字线被共同激活并受到压力，从而集中地对冗余单元和存储器单元进行老化测试。因此，可以减少制造中的老化测试所需的时间。在缺陷测试模式中，冗余字线被依次激活并受到应力，从而执行缺陷检验来检查冗余单元的质量。

80. 发明授权

US6091290A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US6091290A
公开(公告)日：2000-07-18
申请号：US910901
申请日：1997-08-13
申请人： Shinya Fujioka
发明人： Shinya Fujioka
IPC分类号： G11C11/407 , G01R31/30 , G11C11/401 , G11C29/06 , H03K5/08
CPC分类号： G01R31/3004 , H03K5/08
摘要： A semiconductor integrated circuit configured of a DRAM or the like has a function of generating a step-up voltage and supplying it to a plurality of semiconductor devices. During the period when a burn-in test is conducted, the input voltage of a precharge portion for precharging a step-up node for outputting the step-up voltage is clamped to a predetermined level by a precharge input voltage clamping unit. The precharge input voltage clamping unit prevents the step-up voltage level across the step-up node from excessively increasing during the burn-in test.
摘要翻译：由DRAM等构成的半导体集成电路具有产生升压电压并将其提供给多个半导体器件的功能。在进行老化测试的期间中，用于将用于输出升压电压的升压节点预充电的预充电部分的输入电压通过预充电输入电压钳位单元钳位到预定电平。预充电输入电压钳位单元防止升压节点的升压电压在老化测试期间过度增加。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式