专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20100103010A1 TWO-STEP SUB-RANGING ANALOG-TO-DIGITAL CONVERTER AND METHOD FOR PERFORMING TWO-STEP SUB-RANGING IN AN ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：两步式分级模拟数字转换器和在模拟数字转换器中执行两步子范围的方法
公开(公告)号：US20100103010A1
公开(公告)日：2010-04-29
申请号：US12259344
申请日：2008-10-28
申请人： Zailong Zhuang
发明人： Zailong Zhuang
IPC分类号： H03M1/12
CPC分类号： H03M1/1215 , H03M1/122 , H03M1/146 , H03M1/361
摘要： A two-step ADC is provided that achieves significant improvements in the settling time window available for CDAC conversion, FADC sub-ranging and FADC conversion without increasing the amount of chip area or power that are consumed by the ADC. The ADC uses interleaved sampler/buffer circuits to sample the incoming analog signal on different phases of the clock signal. MUXes provide the samples obtained by the sampler/buffer circuits to the CADC and FADC circuits in ping pong fashion in such a way that the CADC and FADC circuits are converting during every clock period. In addition, these improvements are achieved without increasing the number of potential sources of bit decision mismatches in the two-step sub-ranging ADC.
摘要翻译：提供了两步ADC，可以实现CDAC转换，FADC子范围和FADC转换可用的建立时间窗口的显着改进，而不增加ADC消耗的芯片面积或功耗。 ADC使用交错采样器/缓冲电路在时钟信号的不同相位上对输入模拟信号进行采样。 MUX以采样/缓冲电路获得的样本以乒乓方式将CADC和FADC电路以CADC和FADC电路在每个时钟周期内进行转换。此外，这些改进是在不增加两步子范围ADC中的位决策不匹配的潜在来源的数量的情况下实现的。

72. 发明授权

US07613901B2 Comparators in IC with programmably controlled positive / negative hysteresis level and open-drain / push-pull output coupled to crossbar switch or rising / falling edge interrupt generation 有权
标题翻译： IC中的比较器具有可编程控制的正/负滞后电平和开漏/推挽输出，连接到交叉开关或上升/下降沿中断产生
公开(公告)号：US07613901B2
公开(公告)日：2009-11-03
申请号：US11694629
申请日：2007-03-30
申请人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R. Holberg
发明人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R. Holberg
IPC分类号： G06F19/00 , H03K5/22
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A plurality of comparators perform compare operations within the integrated circuit package. At least one control register is associated with each of the plurality of comparators, and each of the plurality of comparators are software programmable to control a hysteresis of the comparators responsive to control bits established in the at least one control register of the comparator by the processing core. An amount of positive hysteresis is programmed via a first group of the control bits and an amount of negative hysteresis is programmed via a second group of the control bits.
摘要翻译：集成电路封装包括用于对一组指令进行操作以执行预定义的处理的处理核心。多个比较器执行集成电路封装内的比较操作。至少一个控制寄存器与多个比较器中的每个比较器相关联，并且多个比较器中的每一个可软件编程以响应于通过处理在比较器的至少一个控制寄存器中建立的控制位来控制比较器的滞后核心。通过第一组控制位来编程正滞后量，经由第二组控制位来编程负滞后量。

73. 发明授权

US07319419B1 Switched capacitor circuit with current source offset DAC and method 有权
标题翻译：具有电流源偏移DAC和方法的开关电容电路
公开(公告)号：US07319419B1
公开(公告)日：2008-01-15
申请号：US11512389
申请日：2006-08-30
申请人： Christopher P. Lash , Ronald F. Cormier, Jr. , Frederick J. Highton
发明人： Christopher P. Lash , Ronald F. Cormier, Jr. , Frederick J. Highton
IPC分类号： H03M1/06
CPC分类号： H03M1/0607 , H03M1/122 , H03M1/745
摘要： A switched-capacitor sample/hold circuit includes a switched-capacitor input sampling stage and a sample/hold amplifier circuit including an operational amplifier having first and second inputs coupled to first and second input sampling capacitors, respectively, and first and second feedback capacitors coupled between the first and second inputs and first and second outputs of the operational amplifier. A continuous-time offset DAC receives a digital input signal representative of an offset voltage produces first and second offset correction voltages. The first and second offset correction voltages are coupled to the switched-capacitor sample/hold circuit to adjust the amount of pre-charging of the first and second feedback capacitors, respectively, in accordance with the value of the digital input signal to compensate an offset component associated with the and second input voltages. The output of the switched-capacitor sample/hold circuit can be connected to an ADC.
摘要翻译：开关电容器采样/保持电路包括开关电容器输入采样级和采样/保持放大器电路，其包括运算放大器，该运算放大器分别具有耦合到第一和第二输入采样电容器的第一和第二输入端，并且耦合第一和第二反馈电容器在第一和第二输入与运算放大器的第一和第二输出之间。连续时间偏移DAC接收代表偏移电压的数字输入信号产生第一和第二偏移校正电压。第一和第二偏移校正电压被耦合到开关电容器采样/保持电路，以分别根据数字输入信号的值来调整第一和第二反馈电容器的预充电量，以补偿偏移与第二输入电压相关的分量。开关电容采样/保持电路的输出可以连接到ADC。

74. 发明申请

US20070252744A1 A/D converter device and electronic control apparatus including same 有权
标题翻译： A / D转换装置及包括其的电子控制装置
公开(公告)号：US20070252744A1
公开(公告)日：2007-11-01
申请号：US11790139
申请日：2007-04-24
申请人： Yoshiharu Takeuchi
发明人： Yoshiharu Takeuchi
IPC分类号： H03M1/12
CPC分类号： H03M1/1076 , H03M1/122 , H03M1/36
摘要： The A/D converter device includes a comparing section and an abnormality judging section. The comparing section compares a voltage of its signal transfer line connected between its input multiplexer and its A/D converting section through its sample-hold section with a predetermined abnormality judging voltage. The abnormality judging section is configured to apply a reference voltage to the signal transfer line in synchronization with an A/D conversion cycle thereof on condition that its A/D converting operation thereof is not interrupted, and to determine presence of abnormality in the A/D converter device if an comparison result of the comparing section does not match an expected value corresponding to the reference voltage.
摘要翻译： A / D转换器装置包括比较部分和异常判断部分。比较部分通过其采样保持部分以预定的异常判断电压来比较其输入多路复用器和其A / D转换部分之间连接的信号传输线的电压。异常判定部，其在A / D转换操作未被中断的条件下，与A / D转换周期同步地向信号传送线施加基准电压，并且确定A / 如果比较部分的比较结果与对应于参考电压的期望值不匹配，则D转换器装置。

75. 发明申请

US20070189419A1 Conversion of multiple analog signals in an analog to digital converter 有权
标题翻译：在模数转换器中转换多个模拟信号
公开(公告)号：US20070189419A1
公开(公告)日：2007-08-16
申请号：US11352495
申请日：2006-02-10
申请人： Daniel Filipovic
发明人： Daniel Filipovic
IPC分类号： H04L27/00 , H04L27/22 , H04L27/14
CPC分类号： H03M3/472 , H03M1/122
摘要： A multiple analog signal converter (100) simultaneously converts multiple analog signals (104,106) to digital signals (112, 114) using a single analog to digital converter (ADC) 102. A first analog signal (104) at a first center frequency and a second analog signal (106) at a second center frequency are processed by the ADC (102) to generate a composite digital signal (110) comprising a first digital signal (112) corresponding to the first analog signal (104) and a second digital signal (114) corresponding to the second analog signal (106). The composite digital signal (110) is digitally frequency shifted to recover the second digital signal (106). The first digital signal (104) is recovered by digitally filtering the composite digital signal (110). In some circumstances, a first radio frequency (RF) signal (118) and a second RF signal (122) are frequency shifted to generate the first analog signal (104) and second analog signal (106).
摘要翻译：多模拟信号转换器（100）使用单个模数转换器（ADC）102同时转换多个模拟信号（104,106）到数字信号（112,114）。第一中心频率的第一模拟信号（104）和第二中心频率的第二模拟信号（106）由ADC（102）处理以产生包括第一数字信号（112）的复合数字信号（110）对应于第一模拟信号（104）和对应于第二模拟信号（106）的第二数字信号（114）。复合数字信号（110）被数字频移以恢复第二数字信号（106）。通过数字滤波复合数字信号（110）来恢复第一数字信号（104）。在某些情况下，第一射频（RF）信号（118）和第二RF信号（122）被频移以产生第一模拟信号（104）和第二模拟信号（106）。

76. 发明申请

US20070103357A1 ANALOG-TO-DIGITAL CONVERTER WITH LOW POWER TRACK-AND-HOLD MODE 有权
标题翻译：具有低功率跟踪和保持模式的模拟数字转换器
公开(公告)号：US20070103357A1
公开(公告)日：2007-05-10
申请号：US11618644
申请日：2006-12-29
申请人： DONALD ALFANO , DANNY ALLRED , DOUGLAS PIASECKI , KENNETH FERNALD , KA LEUNG , BRIAN CALOWAY , ALVIN STORVIK , PAUL HIGHLEY , DOUGLAS HOLBERG
发明人： DONALD ALFANO , DANNY ALLRED , DOUGLAS PIASECKI , KENNETH FERNALD , KA LEUNG , BRIAN CALOWAY , ALVIN STORVIK , PAUL HIGHLEY , DOUGLAS HOLBERG
IPC分类号： H03M1/12
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A method for converting analog data to digital data is disclosed. The method includes operating an analog-to-digital data converter in a tracking mode to sample an input signal and in a convert mode to convert the sampled input signal after sampling to a digital signal. The analog-to-digital data converter is controlled with a controller to operate in different modes of operation by providing at least one step wherein the tracking mode of operation is controlled to initiate at a predetermined time to begin the sampling operation.
摘要翻译：公开了一种将模拟数据转换为数字数据的方法。该方法包括以跟踪模式操作模拟数字数据转换器，以对输入信号进行采样，并以转换模式对采样后的采样输入信号进行数字信号转换。模拟数字数据转换器由控制器控制，以通过提供至少一个步骤操作在不同的操作模式，其中跟踪操作模式被控制以在预定时间开始以开始采样操作。

77. 发明授权

US07136005B1 Accurate low noise analog to digital converter system 有权
标题翻译：精确的低噪声模数转换器系统
公开(公告)号：US07136005B1
公开(公告)日：2006-11-14
申请号：US11122587
申请日：2005-05-05
申请人： Colin G. Lyden , Michael C. Coln , Robert Brewer
发明人： Colin G. Lyden , Michael C. Coln , Robert Brewer
IPC分类号： H03M1/50
CPC分类号： H03M1/08 , H03M1/122
摘要： An accurate, low noise conditionally resetting integrator circuit in an analog to digital system samples, with an analog to digital converter, the output of an integrating circuit a number of times during a measuring period; isolates the input for the integrating circuit during sample event; generates a reset signal in response to the integrating circuit output reaching a predetermined level; and resets the feedback capacitor of the integrating circuit by isolating it from the amplifier circuit of the integrating circuit and connecting it to a reference source during a sample event.
摘要翻译：模拟数字系统中的精确低噪声有条件复位积分电路采样模数转换器，在测量期间多次输出积分电路; 在采样事件期间隔离积分电路的输入; 响应于所述积分电路输出达到预定水平而产生复位信号; 并且通过将其与积分电路的放大器电路隔离并且在采样事件期间将其连接到参考源来复位积分电路的反馈电容器。

78. 发明授权

US4851843A Analogue-to-digital conversion apparatus 失效
标题翻译：模数转换装置
公开(公告)号：US4851843A
公开(公告)日：1989-07-25
申请号：US244597
申请日：1988-09-13
申请人： Martin Neal
发明人： Martin Neal
IPC分类号： H03M1/18 , H03M1/00
CPC分类号： H03M1/0619 , H03M1/122 , H03M1/16
摘要： Apparatus including an analogue-to-digital converter 26 having a given number of digits, includes a variable gain amplifier (23) for the input (VA) to the converter (26). If any one instantaneous value (21A) of the input (VA) is less than is necessary to saturate the converter (26), i.e. to use all the digits of the converter (26), the gain of the amplifier (23) is automatically set to amplify the instantaneous input (21A) to the extent necessary to saturate the converter (26). By such selective amplication of different outputs (VA), each instantaneous value (21A) is digitized by the full number of digits of the converter (26) and the resolution of the apparatus is the same for all inputs (VA) regardless of their magnitude. On the other hand the converter is not over-saturated such as could be the case if the different inputs (VA) were amplified by a common gain.
摘要翻译：包括具有给定数量位数的模拟 - 数字转换器26的装置包括用于到转换器（26）的输入（VA）的可变增益放大器（23）。如果输入（VA）的任何一个瞬时值（21A）小于使转换器（26）饱和，即使用转换器（26）的所有数字所必需的，则放大器（23）的增益将自动地设置为将瞬时输入（21A）放大到使转换器（26）饱和所必需的程度。通过不同输出（VA）的这种选择性放大，每个瞬时值（21A）被转换器（26）的全数位数字化，并且对于所有输入（VA）而言，该装置的分辨率是相同的，而与其幅度无关。另一方面，转换器不会过饱和，如果不同的输入（VA）被公共增益放大，则可能会出现这种情况。

79. 发明授权

US11646748B2 ML-based phase current balancer 有权
公开(公告)号：US11646748B2
公开(公告)日：2023-05-09
申请号：US16841213
申请日：2020-04-06
申请人： Infineon Technologies Austria AG
发明人： Benjamin Schwabe , Salman Nazir , David Williams
IPC分类号： H03M1/48 , H03M1/12 , H02M3/04
CPC分类号： H03M1/122 , H02M3/04
摘要： A machine learning (ML)-based phase current balancer for a multiphase power converter includes one or more inputs, one or more outputs, and an artificial neural network. The artificial neural network includes a plurality of artificial neurons and is trained to provide corrective phase current imbalance information at the one or more outputs for correcting phase current imbalance within the multiphase power converter, based on information available at the one or more inputs and indicative of individual phase currents of the multiphase power converter.

80. 发明申请

US20180069576A1 Time Sequenced Spectral Stitching 审中-公开
公开(公告)号：US20180069576A1
公开(公告)日：2018-03-08
申请号：US15692596
申请日：2017-08-31
申请人： NATIONAL INSTRUMENTS CORPORATION
发明人： Stephen L. Dark , Christopher N. White
IPC分类号： H04B1/10 , H04L7/00
CPC分类号： H04B1/10 , G01R13/0272 , H03M1/122 , H04L7/0029 , H04L7/0041 , H04L7/0087 , H04L25/022 , H04L27/3827
摘要： Methods and systems are disclosed for using a single receiving device, such as a single VSA, to capture and digitize multiple time-domain acquisitions of a repeating signal at different center frequencies, to create a single time-domain waveform having a bandwidth greater than the real-time instantaneous bandwidth of the receiving device. Specifically, one or more signal processing paths may process the multiple digitized acquisitions of the repeating signal, either sequentially or in parallel, such that the processed acquisitions may be aggregated into a representation of one or more repetitions of the repeating signal.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式