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71. 发明申请

US20150228546A1 SEMICONDUCTOR DEVICE AND METHOD OF REMOVING SPACERS ON SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件和半导体器件上的间隔元件的移除方法
公开(公告)号：US20150228546A1
公开(公告)日：2015-08-13
申请号：US14177233
申请日：2014-02-11
申请人： UNITED MICROELECTRONICS CORP.
发明人： Yu-Chun Huang , Shin-Chuan Huang , Tung-Ming Chen
IPC分类号： H01L21/8238 , H01L29/78 , H01L21/311 , H01L27/092
CPC分类号： H01L21/823864 , H01L21/31105 , H01L21/31144 , H01L21/823807 , H01L27/0928 , H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A manufacturing method for a semiconductor device includes: providing a substrate including a first gate structure disposed thereon, wherein the first gate structure includes a first gate electrode and a first hard mask covers the first gate electrode. A first oxide spacer and a silicon carbon nitride spacer are formed in sequence to surround the first gate electrode. A thermal treatment is performed to form a silicon oxycarbonitride layer between the first oxide spacer and the silicon carbon nitride spacer. Then, a second oxide spacer, a third oxide spacer, and a first silicon nitride spacer are formed on the silicon carbon nitride spacer in sequence. The first hard mask and the first silicon nitride spacer are removed. Finally, the third oxide spacer, the second oxide spacer, and silicon carbon nitride spacer are removed entirely to expose the silicon oxycarbonitride layer.
摘要翻译：半导体器件的制造方法包括：提供包括设置在其上的第一栅极结构的衬底，其中所述第一栅极结构包括第一栅电极和第一硬掩模覆盖所述第一栅电极。依次形成第一氧化物间隔物和硅氮化物间隔物以包围第一栅电极。进行热处理以在第一氧化物间隔物和硅氮化硅间隔物之间形成硅碳氮氧化物层。然后依次在硅氮化物间隔物上形成第二氧化物间隔物，第三氧化物间隔物和第一氮化硅间隔物。去除第一硬掩模和第一氮化硅间隔物。最后，完全除去第三氧化物间隔物，第二氧化物间隔物和硅氮化物间隔物以露出硅碳氮氧化物层。

72. 发明授权

US09093499B2 Integrated circuit using FDSOI technology, with well sharing and means for biasing oppositely doped ground planes present in a same well 有权
标题翻译：使用FDSOI技术的集成电路，具有良好的共享和用于偏置存在于同一井中的相反掺杂的接地平面的装置
公开(公告)号：US09093499B2
公开(公告)日：2015-07-28
申请号：US13627059
申请日：2012-09-26
申请人： Jean-Philippe Noel , Bastien Giraud , Olivier Thomas
发明人： Jean-Philippe Noel , Bastien Giraud , Olivier Thomas
IPC分类号： H01L29/66 , H01L29/786 , H01L21/768 , H01L21/84 , H01L27/12 , H01L27/092 , H01L21/8238
CPC分类号： H01L21/768 , H01L21/823892 , H01L21/84 , H01L27/0928 , H01L27/1203 , H01L29/78609 , H01L29/78648
摘要： A manufacture includes an IC comprising a stacking of a semiconducting substrate, a buried insulating layer, and a semiconducting layer, a first electronic component formed in and/or on the semiconductor layer, a bias circuit to generate a first bias voltage, first and second via-type interconnections, to which the bias circuit applies a same bias voltage equal to the first bias voltage, a first insulation trench separating the first electronic component from the first and second interconnections, a first ground plane having a first type of doping, placed beneath the buried insulating layer plumb with the first electronic component, and extending beneath the first insulation trench and up into contact the first interconnection, and a first well having a second type of doping opposite that of the first type, plumb with the first ground plane, and extending beneath the first insulation trench and up into contact with the second interconnection.
摘要翻译：一种制造方法包括：IC，其包括半导体衬底，掩埋绝缘层和半导体层的堆叠;形成在半导体层中和/或上的半导体层的第一电子部件;产生第一偏置电压的偏置电路;第一和第二偏置电路施加与第一偏置电压相同的偏置电压的通孔型互连，将第一电子部件与第一和第二互连分开的第一绝缘沟槽，具有第一类型的掺杂的第一接地平面在第一电子部件的埋置绝缘层铅垂之下，并且在第一绝缘沟槽下方延伸并且与第一互连接触，并且具有与第一类型相反的第二类型掺杂的第一阱具有第一接地层并且在第一绝缘沟槽下方延伸并与第二互连接触。

73. 发明申请

US20150206880A1 HIGH VOLTAGE LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LDMOSFET) HAVING A DEEP FULLY DEPLETED DRAIN DRIFT REGION 有权
公开(公告)号：US20150206880A1
公开(公告)日：2015-07-23
申请号：US14672865
申请日：2015-03-30
申请人： International Business Machines Corporation
发明人： John B. Campi, JR. , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Souvick Mitra , Mujahid Muhammad
IPC分类号： H01L27/092 , H01L29/10 , H01L29/08 , H01L29/78
CPC分类号： H01L27/0928 , H01L21/761 , H01L21/823814 , H01L21/823892 , H01L27/092 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/0878 , H01L29/1045 , H01L29/1087 , H01L29/1095 , H01L29/66659 , H01L29/66681 , H01L29/7801 , H01L29/7816 , H01L29/7835
摘要： Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.

74. 发明申请

US20150187594A1 Composite Structure for Gate Level Inter-Layer Dielectric 有权
标题翻译：栅极层间介质的复合结构
公开(公告)号：US20150187594A1
公开(公告)日：2015-07-02
申请号：US14141028
申请日：2013-12-26
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Che-Hao Tu , William Weilun Hong , Ying-Tsung Chen
IPC分类号： H01L21/3105 , H01L27/092 , H01L29/66
CPC分类号： H01L21/31055 , H01L21/31053 , H01L21/76224 , H01L21/823462 , H01L21/823481 , H01L21/823878 , H01L27/088 , H01L27/092 , H01L27/0928 , H01L29/66545
摘要： A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to recede the first dielectric layer to the height of the dummy gates, etching to recess the first dielectric layer below the height of the gates, depositing one or more additional dielectric layers over the first dielectric layer, and chemical mechanical polishing to recede the one or more additional dielectric layers to the height of the gates. The method provides integrated circuit devices having metal gate electrodes and an inter-level dielectric at the gate level that includes a capping layer. The capping layer resists etching and preserves the gate height through a replacement gate process.
摘要翻译：形成集成电路器件的方法包括在半导体衬底上形成伪栅极，在虚拟栅极上沉积第一介电层，化学机械抛光以将第一介电层退回到虚拟栅极的高度，蚀刻以使第一电介质在栅极的高度以下，在第一介电层上沉积一个或多个附加电介质层，以及化学机械抛光以将一个或多个另外的介电层退回到栅极的高度。该方法提供了集成电路器件，其具有金属栅极电极和栅极电平处的包括封盖层的级间电介质。封盖层抵抗蚀刻并通过替换浇口工艺保持浇口高度。

75. 发明申请

US20150179650A1 FLOATING BODY MEMORY CELL HAVING GATES FAVORING DIFFERENT CONDUCTIVITY TYPE REGIONS 有权
标题翻译：具有不同电导率类型区域的浮动体内存单元
公开(公告)号：US20150179650A1
公开(公告)日：2015-06-25
申请号：US14641167
申请日：2015-03-06
申请人： Peter L. D. Chang , Uygar E. Avci , David Kencke , Ibrahim Ban
发明人： Peter L. D. Chang , Uygar E. Avci , David Kencke , Ibrahim Ban
IPC分类号： H01L27/108 , H01L29/66 , H01L21/28 , H01L29/78
CPC分类号： H01L27/10802 , H01L21/28008 , H01L21/823821 , H01L21/823828 , H01L21/823857 , H01L21/823878 , H01L21/823892 , H01L27/0924 , H01L27/0928 , H01L27/108 , H01L27/10826 , H01L27/10844 , H01L27/10879 , H01L27/1203 , H01L29/0649 , H01L29/0653 , H01L29/16 , H01L29/495 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/66477 , H01L29/66795 , H01L29/78 , H01L29/7841 , H01L29/785 , H01L29/7851 , Y10S257/903
摘要： A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
摘要翻译：描述了一种用于制造浮体记忆单元（FBC）的方法，并且使用其中使用有利于不同导电类型区域的栅极的所得FBC。在一个实施例中，具有更厚绝缘的p型背栅与较薄绝缘的n型前门一起使用。描述了补偿不对准的处理，其允许制造不同的氧化物和栅极材料。

76. 发明授权

US09035392B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09035392B2
公开(公告)日：2015-05-19
申请号：US14185801
申请日：2014-02-20
申请人： Renesas Electronics Corporation
发明人： Nobuhiro Tsuda , Hidekatsu Nishimaki , Hiroshi Omura , Yuko Yoshifuku
IPC分类号： H01L27/092 , H01L27/02 , H01L27/118
CPC分类号： H01L27/0928 , H01L27/0207 , H01L27/092 , H01L27/11803 , H01L27/11898
摘要： A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.
摘要翻译： pMIS区域设置在沿第一方向延伸并且穿过多个标准单元和第一外围边缘中的每一个的边界之间。 nMIS区域设置在边界和第二周边边缘之间。电源布线和接地布线分别沿着第一和第二外围边缘延伸。多个pMIS布线和多个nMIS布线分别布置在沿着第一方向延伸并且沿第二方向以单个间距布置的多个第一虚拟线和多条第二虚拟线上。最接近边界的第一虚拟线和最靠近边界的第二虚拟线之间具有大于单个间距的间距。

77. 发明申请

US20150129971A1 SEMICONDUCTOR ARRANGEMENT FACILITATING ENHANCED THERMO-CONDUCTION 有权
标题翻译：半导体装置促进增强型热导率
公开(公告)号：US20150129971A1
公开(公告)日：2015-05-14
申请号：US14079744
申请日：2013-11-14
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Ming-Hsiang Song , Jam-Wem Lee , Yi-Feng Chang , Wun-Jie Hung Lin
IPC分类号： H01L27/088 , H01L29/66
CPC分类号： H01L27/0251 , H01L21/26513 , H01L21/823437 , H01L21/823493 , H01L21/823828 , H01L21/823871 , H01L21/823892 , H01L27/0207 , H01L27/088 , H01L27/0928 , H01L29/66477
摘要： A semiconductor arrangement includes a well region and a first region disposed within the well region. The first region includes a first conductivity type. The semiconductor arrangement includes a first gate disposed above the well region on a first side of the first region. The first gate includes a first top surface facing away from the well region. The first top surface has a first top surface area. The semiconductor arrangement includes a first gate contact disposed above the first gate. The first gate contact includes a first bottom surface facing towards the well region. The first bottom surface has a first bottom surface area. The first bottom surface area covers at least about two thirds of the first top surface area.
摘要翻译：半导体装置包括阱区和设置在阱区内的第一区。第一区域包括第一导电类型。半导体装置包括设置在第一区域的第一侧上的阱区上方的第一栅极。第一门包括面向远离井区的第一顶面。第一顶表面具有第一顶表面区域。半导体装置包括设置在第一栅极上方的第一栅极触点。第一门接触包括面向井区域的第一底面。第一底表面具有第一底表面区域。第一底表面区域覆盖第一顶表面区域的至少约三分之二。

78. 发明申请

US20150078069A1 INTEGRATED CMOS CIRCUIT HAVING FIRST AND SECOND CIRCUIT PARTS 有权
标题翻译：具有第一和第二电路部件的集成CMOS电路
公开(公告)号：US20150078069A1
公开(公告)日：2015-03-19
申请号：US14478477
申请日：2014-09-05
申请人： STMicroelectronics International N.V.
发明人： Jacques Talayssat
IPC分类号： G11C11/419 , H01L27/11 , G11C8/10
CPC分类号： G11C11/419 , G11C8/10 , H01L21/761 , H01L21/823892 , H01L27/0928 , H01L27/10894 , H01L27/10897 , H01L27/1104
摘要： An integrated circuit includes first and second circuit parts that may be arranged close to one another in a single semiconducting substrate. The circuit may use a deep doping well for reducing digital noise, and may implement a sleep mode for reducing power consumption. This circuit may have a random access memory, and may be a radio communication system-on-chip device. The integrated circuit may advantageously be used within a mobile communication apparatus.
摘要翻译：集成电路包括可以在单个半导体衬底中彼此靠近布置的第一和第二电路部分。电路可以使用深掺杂阱来减少数字噪声，并且可以实现睡眠模式以降低功耗。该电路可以具有随机存取存储器，并且可以是无线电通信片上系统设备。集成电路可以有利地在移动通信设备内使用。

79. 发明申请

US20150054086A1 Semiconductor Device and Method for Manufacturing Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150054086A1
公开(公告)日：2015-02-26
申请号：US14450674
申请日：2014-08-04
申请人： Micron Technology, Inc.
发明人： Kanta SAINO
IPC分类号： H01L27/108 , H01L29/06
CPC分类号： H01L23/5226 , H01L21/761 , H01L21/76229 , H01L21/76834 , H01L21/76838 , H01L21/823462 , H01L21/823481 , H01L21/823871 , H01L21/823878 , H01L21/823892 , H01L27/0928 , H01L27/10814 , H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L29/0649
摘要： A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.
摘要翻译：半导体器件包括设置在半导体衬底内的第一阱和第二阱，设置在半导体衬底内的第一阱和第二阱之间的隔离区，布置在第一阱上的第一布线，设置在第二阱上的第二阱以及设置在所述隔离区域上的凹入的第三布线，设置在所述第三布线上以埋入其凹部的埋入绝缘膜，设置在所述埋入绝缘膜上的多个第四布线，以及布置成电连接到第一和第二孔中的至少一个。

80. 发明授权

US08946826B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08946826B2
公开(公告)日：2015-02-03
申请号：US14179556
申请日：2014-02-13
申请人： Panasonic Corporation
发明人： Masaki Tamaru , Kazuyuki Nakanishi , Hidetoshi Nishimura
IPC分类号： H01L27/092 , H01L27/02 , H01L27/118 , H01L21/8238
CPC分类号： H01L27/11807 , H01L21/823892 , H01L27/0207 , H01L27/0928 , H01L27/11898 , H01L2027/11866 , H01L2027/11881 , H01L2027/1189
摘要： A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
摘要翻译：在电池阵列的N型阱区域中提供阱电位区域。设置在水平方向上的井电位供给区域的两侧的相邻门和设置在其两侧的相邻门以相同的间距设置。此外，相邻单元阵列包括四个栅极，每个栅极在垂直方向上与相邻栅极相对。换句话说，维持在阱电位供给区域的外围的栅极图案的形状的规则性。

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