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71. 发明授权

US08895347B2 Method for fabricating semiconductor layer having textured surface and method for fabricating solar cell 有权
标题翻译：具有纹理表面的半导体层的制造方法和太阳能电池的制造方法
公开(公告)号：US08895347B2
公开(公告)日：2014-11-25
申请号：US13869764
申请日：2013-04-24
申请人： Industrial Technology Research Institute
发明人： Teng-Yu Wang , Chien-Hsun Chen , Chen-Hsun Du , Chung-Yuan Kung
IPC分类号： H01L21/00 , H01L21/30 , H01L31/18 , H01L21/20 , H01L31/0236 , H01L31/068
CPC分类号： H01L31/18 , H01L21/20 , H01L31/02363 , H01L31/068 , Y02E10/52 , Y02E10/547
摘要： The disclosure provides a method for fabricating a semiconductor layer having a textured surface, including: (a) providing a textured substrate; (b) forming at least one semiconductor layer on the textured substrate; (c) forming a metal layer on the semiconductor layer; and (d) conducting a thermal process or a low temperature process to the textured substrate, the semiconductor layer and the metal layer, wherein the semiconductor layer is separated from the textured substrate by the thermal process to obtain the semiconductor layer having the metal layer and a textured surface.
摘要翻译：本公开提供了一种用于制造具有纹理表面的半导体层的方法，包括：（a）提供纹理化衬底; （b）在纹理化衬底上形成至少一个半导体层; （c）在半导体层上形成金属层; 和（d）对纹理化衬底，半导体层和金属层进行热处理或低温工艺，其中半导体层通过热处理与纹理化衬底分离，以获得具有金属层的半导体层和纹理表面。

72. 发明授权

US08815656B2 Semiconductor device and method with greater epitaxial growth on 110 crystal plane 有权
标题翻译：在110晶体平面上具有更大外延生长的半导体器件和方法
公开(公告)号：US08815656B2
公开(公告)日：2014-08-26
申请号：US13622614
申请日：2012-09-19
申请人： International Business Machines Corporation
发明人： Thomas N. Adam , Kangguo Cheng , Judson R. Holt , Keith H. Tabakman , Alexander Reznicek
IPC分类号： H01L21/00 , H01L21/20 , H01L21/02 , H01L21/8238
CPC分类号： H01L21/20 , H01L21/02293 , H01L21/0243 , H01L21/02433 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/823807 , H01L29/045 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A semiconductor processing method is provided which promotes greater growth on crystallographic planes than on other crystallographic planes. Growth rates with the process can be reversed compared to typical epitaxial growth processes such that the highest rate of growth occurs on crystallographic planes and the least amount of growth occurs on crystallographic planes. The process can be applied to form embedded stressor regions in planar field effect transistors, and the process can be used to grow semiconductor layers on exposed wall surfaces of adjacent fins in source-drain regions of finFETs to fill spaces between the fins.
摘要翻译：提供半导体处理方法，其促进在110晶体平面上比在其它晶体平面上更大的生长。与典型的外延生长过程相比，该方法的生长速率可以被逆转，使得在<110>晶面上发生最高生长速率，并且最小量的生长发生在晶体平面上。该方法可以应用于在平面场效应晶体管中形成嵌入的应力区域，并且该工艺可以用于在finFET的源极 - 漏极区域中的相邻鳍片的暴露的壁表面上生长半导体层，以填充鳍片之间的空间。

73. 发明授权

US08809956B2 Vertically oriented semiconductor device and shielding structure thereof 有权
标题翻译：垂直取向的半导体器件及其屏蔽结构
公开(公告)号：US08809956B2
公开(公告)日：2014-08-19
申请号：US13272866
申请日：2011-10-13
申请人： Hsiu-Ying Cho
发明人： Hsiu-Ying Cho
IPC分类号： H01L27/12 , H01L21/20 , H01L21/02
CPC分类号： H01L23/5227 , H01F27/2885 , H01F2027/2809 , H01L21/02 , H01L21/20 , H01L23/5223 , H01L23/5225 , H01L27/016 , H01L27/12 , H01L28/10 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure involves a semiconductor device. The semiconductor device includes a substrate; a capacitor disposed over the substrate; an inductor disposed over the substrate and having a coil feature surrounding the capacitor; and a shielding structure over the substrate and configured around the coil feature.
摘要翻译：本发明涉及半导体器件。半导体器件包括衬底; 设置在所述基板上的电容器; 设置在所述衬底上并且具有围绕所述电容器的线圈特征的电感器; 以及屏蔽结构，并且围绕线圈特征构造。

74. 发明授权

US08759205B2 Semiconductor device and method for manufacturing semiconductor device 有权
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US08759205B2
公开(公告)日：2014-06-24
申请号：US12883463
申请日：2010-09-16
申请人： Tomonori Aoyama , Yusuke Oshiki , Kiyotaka Miyano
发明人： Tomonori Aoyama , Yusuke Oshiki , Kiyotaka Miyano
IPC分类号： H01L29/66 , H01L21/20
CPC分类号： H01L21/20 , H01L29/66
摘要： According to one embodiment, a method for manufacturing a semiconductor device, wherein an amorphous semiconductor film comprising a microcrystal is annealed using a microwave, to crystallize the amorphous semiconductor film comprising the microcrystal using the microcrystal as a nucleus.
摘要翻译：根据一个实施例，一种制造半导体器件的方法，其中使用微波对包含微晶的非晶半导体膜进行退火，以使用微晶作为核使包含微晶的非晶半导体膜结晶。

75. 发明申请

US20140138746A1 PSEUDOMORPHIC HIGH ELECTRON MOBILITY TRANSISTOR COMPRISING DOPED LOW TEMPERATURE BUFFER LAYER 有权
标题翻译：包含低温低温缓冲层的PSEUDOMORPHIC高电子移动晶体管
公开(公告)号：US20140138746A1
公开(公告)日：2014-05-22
申请号：US13679257
申请日：2012-11-16
申请人： AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. L
发明人： Jonathan Abrokwah , Nathan Perkins , John Stanback , Philbert Marsh , Hans G. Rohdin
IPC分类号： H01L29/778 , H01L21/20
CPC分类号： H01L29/778 , H01L21/02395 , H01L21/02463 , H01L21/02546 , H01L21/20 , H01L29/66462 , H01L29/7785
摘要： A pseudomorphic high electron mobility transistor (PHEMT) comprises a substrate comprising a Group III-V semiconductor material, a buffer layer disposed over the substrate, wherein the buffer layer comprises microprecipitates of a Group V semiconductor element and is doped with an N-type dopant, and a channel layer disposed over the buffer layer.
摘要翻译：假型高电子迁移率晶体管（PHEMT）包括包含III-V族半导体材料的衬底，设置在衬底上的缓冲层，其中缓冲层包括V族半导体元件的微沉淀物并掺杂有N型掺杂剂以及设置在缓冲层上的沟道层。

76. 发明授权

US08716052B2 Method for making a structure comprising at least one multi-thick active part 有权
标题翻译：制造包括至少一个多厚活性部分的结构的方法
公开(公告)号：US08716052B2
公开(公告)日：2014-05-06
申请号：US13688746
申请日：2012-11-29
申请人： Commissariat a l'energie atomique et aux energies alternatives
发明人： Philippe Robert
IPC分类号： H01L21/00
CPC分类号： H01L21/20 , B81B2203/0109 , B81B2203/0118 , B81C1/00626 , B81C2201/0115 , B81C2201/019 , G01P15/0802
摘要： A method for making a structure comprising an active part comprising at least two layers from a first single crystal silicon substrate, said method comprising the steps of: a) making at least one porous silicon zone in the first substrate, b) making an epitaxial growth deposition of a single crystal silicon layer on the entire surface of the first substrate and the surface of the porous silicon zone, c) machining the epitaxially grown single crystal layer at the porous silicon zone to make a first suspended zone, d) removing or oxidizing the porous silicon, e) depositing a sacrificial layer being selective towards silicon, f) machining the first substrate, g) releasing the suspended zones by withdrawing the sacrificial layer.
摘要翻译：一种用于制造包括由第一单晶硅衬底至少包含两层的有源部分的结构的方法，所述方法包括以下步骤：a）在所述第一衬底中制备至少一个多孔硅区，b）制备外延生长在第一基板的整个表面和多孔硅区域的表面上沉积单晶硅层，c）在多孔硅区域加工外延生长的单晶层以制成第一悬浮区，d）去除或氧化多孔硅，e）沉积对硅有选择性的牺牲层，f）加工第一衬底，g）通过抽出牺牲层来释放悬浮区。

77. 发明申请

US20140077275A1 Semiconductor Device and Method With Greater Epitaxial Growth on 110 Crystal Plane 有权
标题翻译：半导体器件和方法在110晶面上具有更大的外延生长
公开(公告)号：US20140077275A1
公开(公告)日：2014-03-20
申请号：US13622614
申请日：2012-09-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas N. Adam , Kangguo Cheng , Judson R. Holt , Keith H. Tabakman , Alexander Reznicek
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L21/20 , H01L21/02293 , H01L21/0243 , H01L21/02433 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/823807 , H01L29/045 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A semiconductor processing method is provided which promotes greater growth on crystallographic planes than on other crystallographic planes. Growth rates with the process can be reversed compared to typical epitaxial growth processes such that the highest rate of growth occurs on crystallographic planes and the least amount of growth occurs on crystallographic planes. The process can be applied to form embedded stressor regions in planar field effect transistors, and the process can be used to grow semiconductor layers on exposed wall surfaces of adjacent fins in source-drain regions of finFETs to fill spaces between the fins.
摘要翻译：提供半导体处理方法，其促进在110晶体平面上比在其它晶体平面上更大的生长。与典型的外延生长过程相比，该方法的生长速率可以被逆转，使得在<110>晶面上发生最高生长速率，并且最小量的生长发生在晶体平面上。该方法可以应用于在平面场效应晶体管中形成嵌入的应力区域，并且该工艺可以用于在finFET的源极 - 漏极区域中的相邻鳍片的暴露的壁表面上生长半导体层，以填充鳍片之间的空间。

78. 发明授权

US08652932B2 Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures 有权
标题翻译：具有翅片结构的半导体器件，以及形成具有翅片结构的半导体器件的方法
公开(公告)号：US08652932B2
公开(公告)日：2014-02-18
申请号：US13448749
申请日：2012-04-17
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/76
CPC分类号： H01L29/78 , H01L21/02532 , H01L21/0262 , H01L21/20 , H01L29/66477 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin structures, and at least one gate conductor on the at least one gate dielectric. The sidewall of the gate structure is substantially perpendicular to the upper surface of the substrate surface, wherein the plane defined by the sidewall of the gate structure and a plane defined by an upper surface of the substrate surface intersect at an angle of 90°+/−5°. An epitaxial semiconductor material is in direct contact with the at least two fin structures.
摘要翻译：一种半导体器件，包括在衬底表面上的至少两个鳍结构和存在于所述至少两个鳍结构上的功能栅结构。功能栅极结构包括至少一个与至少两个鳍结构的侧壁直接接触的栅极电介质，以及至少一个栅极电介质上的至少一个栅极导体。栅极结构的侧壁基本上垂直于衬底表面的上表面，其中由栅极结构的侧壁限定的平面和由衬底表面的上表面限定的平面以90°±/ -5°。外延半导体材料与至少两个翅片结构直接接触。

79. 发明申请

US20140008767A1 OXIDE REMOVAL FROM SEMICONDUCTOR SURFACES 有权
标题翻译：氧化硅从半导体表面去除
公开(公告)号：US20140008767A1
公开(公告)日：2014-01-09
申请号：US14005084
申请日：2012-03-14
申请人： Lianhe Li , Alexander Davies , Edmund Linfield
发明人： Lianhe Li , Alexander Davies , Edmund Linfield
IPC分类号： H01L21/02
CPC分类号： H01L21/02661 , B82Y20/00 , H01L21/02 , H01L21/02395 , H01L21/0243 , H01L21/02463 , H01L21/02546 , H01L21/0259 , H01L21/0262 , H01L21/02631 , H01L21/20 , H01L21/306 , H01S5/1231 , H01S5/3412 , H01S2304/02
摘要： A method of removing at least one oxide from a surface of a body of semiconductor material is disclosed, the method comprising: arranging the body in a vacuum chamber; and maintaining a temperature of the body in the vacuum chamber within a predetermined range, or substantially at a predetermined value, while exposing said surface to a flux of indium atoms. Corresponding methods of processing an oxidised surface of a body of semiconductor material to prepare the surface for epitaxial growth of at least one epitaxial layer or film over said surface, and methods of manufacturing a semiconductor device are also disclosed.
摘要翻译：公开了从半导体材料的表面去除至少一种氧化物的方法，所述方法包括：将所述主体布置在真空室中; 以及在使所述表面暴露于铟原子的通量的同时将所述真空室内的体温保持在预定范围内，或基本上保持在预定值。还公开了处理半导体材料体的氧化表面以制备用于在所述表面上至少一个外延层或膜外延生长的表面的相应方法，以及制造半导体器件的方法。

80. 发明申请

US20130126962A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130126962A1
公开(公告)日：2013-05-23
申请号：US13682671
申请日：2012-11-20
申请人： SK hynix Inc.
发明人： Seung Suk OH
IPC分类号： H01L21/20 , H01L29/78
CPC分类号： H01L21/20 , H01L21/823885 , H01L27/1052 , H01L27/10876 , H01L29/41741 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device and a method of manufacturing the same are provided. After spacers are formed on sidewalls of a pillar pattern and a photoresist pattern exposing an OSC formation region is formed on a semiconductor substrate including the pillar pattern and the spacer, processes for removing a spacer corresponding to the OSC formation region to form an OSC, removing the photoresist pattern, forming a bit line between the pillar patterns, an epitaxial layer on the pillar pattern, and forming a vertical gate and a storage node contact, are performed so that the OSC formation process can be simplified. In addition, the OSC formation process is performed in a state that the pillar pattern has a low height so that a failure such as a not-open failure caused in the OSC formation process can be prevented.
摘要翻译：提供半导体器件及其制造方法。在柱状图案的侧壁上形成间隔物之后，在包括柱状图案和间隔物的半导体衬底上形成露出OSC形成区域的光致抗蚀剂图案，除去与OSC形成区域相对应的间隔物以形成OSC，去除在柱状图案之间形成位线，在柱状图案上形成外延层，形成垂直栅极和存储节点接触的光致抗蚀剂图案，可以简化OSC形成处理。此外，OSC形成处理在柱状图形具有低高度的状态下进行，从而可以防止在OSC形成处理中引起的诸如不打开故障之类的故障。

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