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71. 发明申请

US20150067301A1 MICROPROCESSOR WITH BOOT INDICATOR THAT INDICATES A BOOT ISA OF THE MICROPROCESSOR AS EITHER THE X86 ISA OR THE ARM ISA 有权
标题翻译：具有引导指示器的微处理器显示了作为X86 ISA或ARM ISA的微处理器的引导ISA
公开(公告)号：US20150067301A1
公开(公告)日：2015-03-05
申请号：US14526029
申请日：2014-10-28
申请人： VIA TECHNOLOGIES, INC.
发明人： G. GLENN HENRY , TERRY PARKS , RODNEY E. HOOKER
IPC分类号： G06F15/82 , G06F9/38 , G06F9/30
CPC分类号： G06F9/441 , G06F9/265 , G06F9/30043 , G06F9/30072 , G06F9/30076 , G06F9/30105 , G06F9/30123 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/3802 , G06F9/4401 , G06F9/4403 , G06F15/82
摘要： A microprocessor includes a plurality of registers that holds an architectural state of the microprocessor and an indicator that indicates a boot instruction set architecture (ISA) of the microprocessor as either the x86 ISA or the Advanced RISC Machines (ARM) ISA. The microprocessor also includes a hardware instruction translator that translates x86 ISA instructions and ARM ISA instructions into microinstructions. The hardware instruction translator translates, as instructions of the boot ISA, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal. The microprocessor also includes an execution pipeline, coupled to the hardware instruction translator. The execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. In response to the reset signal, the microprocessor initializes its architectural state in the plurality of registers as defined by the boot ISA prior to fetching the initial ISA instructions.
摘要翻译：微处理器包括保持微处理器架构状态的多个寄存器和指示微处理器的引导指令集体系结构（ISA）作为x86 ISA或高级RISC机器（ARM）ISA的指示符。微处理器还包括硬件指令转换器，将x86 ISA指令和ARM ISA指令转换为微指令。作为引导ISA的指令，硬件指令转换器将转换为接收复位信号后微处理器从架构存储器空间中提取的初始ISA指令。微处理器还包括耦合到硬件指令转换器的执行流水线。执行流水线执行微指令以生成由x86 ISA和ARM ISA指令定义的结果。响应于复位信号，微处理器在获取初始ISA指令之前初始化由引导ISA定义的多个寄存器中的架构状态。

72. 发明授权

US08966226B2 State machine for monitoring a trace port and verifying proper execution of a secure mode entry sequence instruction 有权
标题翻译：用于监视跟踪端口并验证安全模式条目序列指令的正确执行的状态机
公开(公告)号：US08966226B2
公开(公告)日：2015-02-24
申请号：US10961748
申请日：2004-10-08
申请人： Gregory Remy Philippe Conti , Jerome Laurent Azema
发明人： Gregory Remy Philippe Conti , Jerome Laurent Azema
IPC分类号： G06F9/00 , G06F11/30 , G06F11/28 , G06F21/00 , G06F9/30 , G06F21/82
CPC分类号： G06F21/6209 , G06F9/30076 , G06F11/28 , G06F11/3027 , G06F13/4221 , G06F21/00 , G06F21/82
摘要： A method and system of verifying proper execution of a secure mode entry sequence. At least some of the exemplary embodiments may be a method comprising delivering an instruction from a memory to a processor across an instruction bus (the instruction at least partially configures the processor for secure mode of operation different that privilege modes of the processor), verifying delivery of the instruction across the instruction bus, and checking for proper execution of the instruction using a trace port of the processor.
摘要翻译：验证安全模式输入序列的正确执行的方法和系统。示例性实施例中的至少一些可以是包括通过指令总线将指令从存储器递送到处理器的方法（该指令至少部分地配置处理器以确保处理器的特权模式不同于安全操作模式），验证传送的指令，并使用处理器的跟踪端口检查指令的正确执行。

73. 发明申请

US20140380009A1 PROTECTED MEMORY VIEW FOR NESTED PAGE TABLE ACCESS BY VIRTUAL MACHINE GUESTS 审中-公开
标题翻译：受保护的内存视图，用于虚拟机客户访问的页面表
公开(公告)号：US20140380009A1
公开(公告)日：2014-12-25
申请号：US14127561
申请日：2013-06-24
申请人： Michael Lemay , David M. Durham , Ravi L. Sahita , Andrew V. Anderson
发明人： Michael Lemay , David M. Durham , Ravi L. Sahita , Andrew V. Anderson
IPC分类号： G06F12/14 , G06F9/455 , G06F12/10
CPC分类号： G06F12/145 , G06F9/30076 , G06F9/45558 , G06F12/1009 , G06F12/1491 , G06F2009/45583 , G06F2212/1052 , G06F2212/151
摘要： Generally, this disclosure provides systems, methods and computer readable media for a protected memory view in a virtual machine (VM) environment enabling nested page table access by trusted guest software outside of VMX root mode. The system may include an editor module configured to provide access to a nested page table structure, by operating system (OS) kernel components and by user space applications within a guest of the VM, wherein the nested page table structure is associated with one of the protected memory views. The system may also include a page handling processor configured to secure that access by maintaining security information in the nested page table structure.
摘要翻译：通常，本公开提供了用于虚拟机（VM）环境中的受保护的存储器视图的系统，方法和计算机可读介质，其实现了受VMX根模式之外的受信任客户机的嵌套页表访问。该系统可以包括被配置为通过操作系统（OS）内核组件和由VM的来宾内的用户空间应用提供对嵌套页表结构的访问的编辑器模块，其中嵌套页表结构与受保护的内存视图。该系统还可以包括页面处理处理器，其被配置为通过维护嵌套页表结构中的安全信息来保护该访问。

74. 发明授权

US08880851B2 Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline 有权
标题翻译：通过硬件转换执行X86 ISA和arm ISA机器语言程序指令的微处理器由通用执行管道执行的微指令
公开(公告)号：US08880851B2
公开(公告)日：2014-11-04
申请号：US13224310
申请日：2011-09-01
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F9/30 , G06F9/26
CPC分类号： G06F9/441 , G06F9/265 , G06F9/30043 , G06F9/30072 , G06F9/30076 , G06F9/30105 , G06F9/30123 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/3802 , G06F9/4401 , G06F9/4403 , G06F15/82
摘要： A microprocessor includes a hardware instruction translator that translates x86 ISA and ARM ISA machine language program instructions into microinstructions, which are encoded in a distinct manner from the x86 and ARM instructions. An execution pipeline executes the microinstructions to generate x86/ARM-defined results. The microinstructions are distinct from the results generated by the execution of the microinstructions by the execution pipeline. The translator directly provides the microinstructions to the execution pipeline for execution. Each time the microprocessor performs one of the x86 ISA and ARM ISA instructions, the translator translates it into the microinstructions. An indicator indicates either x86 or ARM as a boot ISA. After reset, the microprocessor initializes its architectural state, fetches its first instructions from a reset address, and translates them all as defined by the boot ISA. An instruction cache caches the x86 and ARM instructions and provides them to the translator.
摘要翻译：微处理器包括硬件指令转换器，将x86 ISA和ARM ISA机器语言程序指令转换为微指令，它们以不同于x86和ARM指令的方式进行编码。执行流水线执行微指令以生成x86 / ARM定义的结果。微指令与由执行管道执行微指令生成的结果不同。翻译器直接向执行管道提供微指令以供执行。每当微处理器执行x86 ISA和ARM ISA指令之一时，翻译器将其转换为微指令。指示符指示x86或ARM作为引导ISA。复位后，微处理器初始化其架构状态，从复位地址获取其第一条指令，并按照引导ISA定义将其全部转换。指令缓存缓存x86和ARM指令，并将其提供给翻译器。

75. 发明申请

US20140298335A1 METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR EMULATING VIRTUALIZATION RESOURCES 有权
标题翻译：用于模拟虚拟化资源的方法，系统和计算机可读介质
公开(公告)号：US20140298335A1
公开(公告)日：2014-10-02
申请号：US14224024
申请日：2014-03-24
申请人： Ixia
发明人： Alon Regev , Deepesh Arora , Toshal Dudhwala , Anirban Majumder
IPC分类号： G06F9/455
CPC分类号： G06F11/263 , G06F8/65 , G06F9/30076 , G06F9/45533 , G06F9/45537 , G06F11/203 , G06F11/261 , G06F11/3688
摘要： Methods, systems, and computer readable media for emulating virtualization resources are disclosed. According to one method, the method occurs at a computing platform. The method includes receiving a message associated with a device under test (DUT) and in response to receiving the message, performing an action associated with at least one of an emulated hypervisor and an emulated virtual machine (VM).
摘要翻译：公开了用于模拟虚拟化资源的方法，系统和计算机可读介质。根据一种方法，该方法发生在计算平台上。该方法包括接收与待测设备（DUT）相关联的消息并且响应于接收到该消息，执行与仿真管理程序和仿真虚拟机（VM）中的至少一个相关联的动作。

76. 发明申请

US20140223145A1 Configurable Reduced Instruction Set Core 审中-公开
标题翻译：可配置的减少指令集核心
公开(公告)号：US20140223145A1
公开(公告)日：2014-08-07
申请号：US13992797
申请日：2011-12-30
申请人： INTEL CORPORATION
发明人： Srihari Makineni , Steven R. King , Zhen Fang , Alexander Redkin , Ravishankar Iyer , Pavel S. Smirnov , Dmitry Gusev , Dmitri Pavlov , May Wu
IPC分类号： G06F9/30
CPC分类号： G06F9/30076 , G06F1/32 , G06F9/30196 , G06F9/3822 , G06F9/3891
摘要： A processor may be built with cores that only execute some partial set of the instructions needed to be fully backwards compliant. Thus, in some embodiments power consumption may be reduced by providing partial cores that only execute certain instructions and not other instructions. The instructions not supported may be handled in other, more energy efficient ways, so that, the overall processor, including the partial core, may be fully backwards compliant.
摘要翻译：处理器可以用仅执行需要完全向后兼容的一些部分指令集的核来构建。因此，在一些实施例中，可以通过提供仅执行特定指令而不是其他指令的部分核来降低功耗。不支持的指令可以以其他更节能的方式处理，使得包括部分核心的整体处理器可以完全向后兼容。

77. 发明申请

US20140165049A1 COMPILER-CONTROLLED REGION SCHEDULING FOR SIMD EXECUTION OF THREADS 有权
标题翻译：用于SIMD执行螺纹的编译器控制区域调度
公开(公告)号：US20140165049A1
公开(公告)日：2014-06-12
申请号：US13710279
申请日：2012-12-10
申请人： NVIDIA CORPORATION
发明人： Gregory DIAMOS , Mojtaba MEHRARA
IPC分类号： G06F9/45
CPC分类号： G06F9/30076 , G06F8/443 , G06F8/453 , G06F9/3851
摘要： A compiler-controlled technique for scheduling threads to execute different regions of a program. A compiler analyzes program code to determine a control flow graph for the program code. The control flow graph contains regions and directed edges between regions. The regions have associated execution priorities. The directed edges indicate the direction of program control flow. Each region has a thread frontier which contains one or more regions. The compiler inserts one or more update predicate mask variable instructions at the end of a region. The compiler also inserts one or more conditional branch instructions at the end of the region. The conditional branch instructions are arranged in order of execution priority of the regions in the thread frontier of the region, to enforce execution priority of the regions at runtime.
摘要翻译：用于调度线程以执行程序的不同区域的编译器控制的技术。编译器分析程序代码以确定程序代码的控制流程图。控制流程图包含区域之间的区域和有向边。这些区域具有相关的执行优先级。有向边缘表示程序控制流程的方向。每个区域都有一个线程，它包含一个或多个区域。编译器在区域的末尾插入一个或多个更新谓词掩码变量指令。编译器还在该区域的末尾插入一个或多个条件分支指令。条件分支指令按照该区域的线程前沿区域的执行优先级的顺序排列，以在运行时强制区域的执行优先级。

78. 发明授权

US08751774B2 Method and system for controlling message traffic between two processors 有权
标题翻译：用于控制两个处理器之间的消息流量的方法和系统
公开(公告)号：US08751774B2
公开(公告)日：2014-06-10
申请号：US13077689
申请日：2011-03-31
申请人： Wan-ping Yang , Koji Shinoda , Hiroaki Shibata
发明人： Wan-ping Yang , Koji Shinoda , Hiroaki Shibata
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30 , G06F9/30076 , G06F15/163
摘要： A system and method for controlling messaging between a first processor and a second processor is disclosed. The second processor controls one or more peripheral devices on behalf of a plurality of predetermined tasks being executed by the first processor. The system includes a message control module that receives an input message intended for the second processor from the first processor and maintains a message history based on the received input message and previously received input messages. The message history indicates which peripheral devices of the system are to be on and which tasks of the plurality of tasks requested the peripheral devices to be on. The message control module is further configured to generate an output message that includes output instructions for the second processor based on the message history and an output duration based on the message history. The second processor executes the output instructions.
摘要翻译：公开了一种用于控制第一处理器和第二处理器之间的消息传递的系统和方法。第二处理器代表由第一处理器执行的多个预定任务来控制一个或多个外围设备。该系统包括消息控制模块，其从第一处理器接收针对第二处理器的输入消息，并且基于接收到的输入消息和先前接收的输入消息来维护消息历史。消息历史指示系统的哪些外围设备将要打开，并且多个任务的哪些任务请求外围设备打开。消息控制模块还被配置为基于消息历史和基于消息历史的输出持续时间来生成包括用于第二处理器的输出指令的输出消息。第二个处理器执行输出指令。

79. 发明申请

US20140095848A1 Tracking Operand Liveliness Information in a Computer System and Performing Function Based on the Liveliness Information 审中-公开
标题翻译：基于活力信息跟踪操作员活动度计算机系统和执行功能的信息
公开(公告)号：US20140095848A1
公开(公告)日：2014-04-03
申请号：US14100077
申请日：2013-12-09
申请人： International Business Machines Corporation
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/38
CPC分类号： G06F9/3834 , G06F9/30076 , G06F9/30105 , G06F9/30127 , G06F9/30185 , G06F9/3832 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/462
摘要： Operand liveness state information is maintained during context switches for current architected operands of executing programs the current operand state information indicating whether corresponding current operands are any one of enabled or disabled for use by a first program module, the first program module comprising machine instructions of an instruction set architecture (ISA) for disabling current architected operands, wherein a current operand is accessed by a machine instruction of said first program module, the accessing comprising using the current operand state information to determine whether a previously stored current operand value is accessible by the first program module.
摘要翻译：操作数活动状态信息在用于执行程序的当前构造操作数的上下文切换期间被维持，当前操作数状态信息指示相应的当前操作数是否是由第一程序模块使用或禁用的任何一个，第一程序模块包括机器指令指令集架构（ISA），用于禁用当前的架构操作数，其中当前操作数由所述第一程序模块的机器指令访问，所述访问包括使用当前操作数状态信息来确定先前存储的当前操作数值是否可被第一个程序模块。

80. 发明授权

US08683261B2 Out of order millicode control operation 失效
标题翻译：无序控制操作
公开(公告)号：US08683261B2
公开(公告)日：2014-03-25
申请号：US13186953
申请日：2011-07-20
申请人： Michael Cremer , Guenter Gerwig , Frank Lehnert , Peter Probst
发明人： Michael Cremer , Guenter Gerwig , Frank Lehnert , Peter Probst
IPC分类号： G06F11/00
CPC分类号： G06F9/30076 , G06F9/30101 , G06F9/3838 , G06F9/3863
摘要： Instructions within a processor are managed by receiving, at a recovery unit of the processor, an instruction that modifies a control register residing within the recovery unit. The recovery unit receives a first set of data associated with the instruction from a general register. A second set of data associated with the instruction is retrieved from the control register by the recovery unit. The recovery unit performs at least one binary logic operation on the first set of data and the second data.
摘要翻译：在处理器中的指令通过在处理器的恢复单元处接收修改驻留在恢复单元内的控制寄存器的指令来管理。恢复单元从通用寄存器接收与该指令相关联的第一组数据。与指令相关联的第二组数据由恢复单元从控制寄存器检索。恢复单元对第一组数据和第二数据执行至少一个二进制逻辑运算。

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