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    • 72. 发明申请
    • A METHOD AND A DEVICE FOR MEASURING PARAMETERS OF AN ANALOG SIGNAL
    • 一种用于测量模拟信号参数的方法和装置
    • US20160209449A1
    • 2016-07-21
    • US14915268
    • 2014-08-29
    • UNIWERSYTET JAGIELLONSKI
    • Marek PALKAPawel MOSKAL
    • G01R19/175G01T1/29
    • G01R19/175G01T1/2985G04F10/005G06F1/00G06F2101/00H01L21/00
    • A method for measuring parameters of an analog signal to determine times at which the analog signal (S) crosses pre-determined voltage thresholds (VA, VB, VC, VD), the method comprising the steps of: splitting the analog signal (S) into a number of interim signals (SA, SB, SC, SD), the number of the interim signals corresponding to the number of the preset voltage thresholds (VA, VB, VC, VD); providing an FPGA system (10) comprising differential buffers (11A, 11B, 11C, 11D) with outputs connected to a number of sequences (20A, 20B, 20C, 20D) of delay elements (21, 22, 23), the number of sequences of delay elements corresponding to the number of the preset voltage thresholds (VA, VB, VC, VD); inputting, to an input of each differential buffer (11A, 11B, 11C, 11D), one interim signal (SA, SB, SC, SD) and a reference voltage corresponding to a particular preset voltage threshold (VA, VB, VC, VD); reading, by means of vector generators (31A, 31B, 31C, 31D), assigned separately to each of the sequences (20A, 20B, 20C, 20D) and connected to a common clock signal (CLK), current values of output signals of each of the delay elements (21, 22, 23) in the particular sequence (20A, 20B, 20C, 20D) at the same moment for all vector generators and providing these values as sequence output vectors (WA, WB, WC, WD); and determining times at which the analog signal (S) crosses the predetermined voltage thresholds (VA, VB, VC, VD) on the basis of the values of the sequence output vectors (WA, WB, WC, WD) and the delays introduced by the delay elements (21, 22, 23).
    • 一种用于测量模拟信号的参数以确定模拟信号(S)跨越预定电压阈值(VA,VB,VC,VD)的时间的方法,所述方法包括以下步骤:将模拟信号(S) 转换成多个中间信号(SA,SB,SC,SD),与预设电压阈值(VA,VB,VC,VD)的数量对应的中间信号的数量; 提供包括差分缓冲器(11A,11B,11C,11D)的FPGA系统(10),其具有连接到多个延迟元件(20A,20B,20C,20D)的延迟元件(20A,20B,20C,20D)的数量, 对应于预设电压阈值(VA,VB,VC,VD)的数量的延迟元件的序列; 向每个差分缓冲器(11A,11B,11C,11D)的输入端输入一个中间信号(SA,SB,SC,SD)和对应于特定预设电压阈值(VA,VB,VC,VD ); 通过分别分配给每个序列(20A,20B,20C,20D)并连接到公共时钟信号(CLK)的矢量发生器(31A,31B,31C,31D)读取,输出信号的电流值 对于所有矢量发生器,在同一时刻对特定序列(20A,20B,20C,20D)中的每个延迟元件(21,22,23)提供这些值作为序列输出向量(WA,WB,WC,WD) ; 以及基于序列输出向量(WA,WB,WC,WD)的值和延迟引起的延迟来确定模拟信号(S)跨越预定电压阈值(VA,VB,VC,VD)的时间 延迟元件(21,22,23)。
    • 80. 发明授权
    • High-performance zero-crossing detector
    • 高性能零交叉检测器
    • US08884656B2
    • 2014-11-11
    • US14061830
    • 2013-10-24
    • Sigma Designs Israel S.D.I Ltd.
    • Danny Braunshtein
    • H03K5/1536G01R19/175
    • G01R19/175H03K5/1536
    • A zero-crossing detection circuit includes a comparator and circuitry. The comparator produces an output signal that is indicative of zero-crossing events in an input Alternating Current (AC) waveform. The circuitry may be configured to feed the comparator with first and second rails voltages, and to progressively increase the rails voltages during time intervals derived from the input AC waveform, so as to feed the comparator with target values of the rails voltages in time-proximity to the zero-crossing events. The circuitry may be configured to compensate for an error in detecting the zero crossing events caused by differences in amplitude of the input AC waveform, by correcting the input AC waveform provided to the comparator. The circuitry may be configured to activate the comparator during time intervals preceding respective anticipated times of the zero-crossing events, and to deactivate the comparator at least once during time periods other than the time intervals.
    • 过零检测电路包括比较器和电路。 比较器产生一个输出信号,其表示输入交流(AC)波形中的过零事件。 电路可以被配置为将比较器馈送到第一和第二轨道电压,并且在从输入AC波形导出的时间间隔期间逐渐增加轨道电压,以便将比较器的轨迹电压的目标值馈送到时间接近 到零交叉事件。 电路可以被配置为通过校正提供给比较器的输入AC波形来补偿检测由输入AC波形的幅度差异引起的过零事件的误差。 电路可以被配置为在过零事件的相应预期时间之前的时间间隔期间激活比较器,并且在时间间隔之外的时间段期间停用比较器至少一次。