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71. 发明授权

US09755512B2 Digital auto compensation for voltage regulators 有权
公开(公告)号：US09755512B2
公开(公告)日：2017-09-05
申请号：US14853713
申请日：2015-09-14
申请人： INTERSIL AMERICAS LLC
发明人： Shuai Jiang , Zhixiang Liang , Jian Yin
IPC分类号： H02M3/157 , H02M1/00
CPC分类号： H02M3/157 , H02M2001/0025
摘要： Auto-compensation—for compensating voltage regulators generating a regulated output voltage—may be performed dynamically by determining various coefficients of a compensation function used in compensating the power regulator, based at least on assumptions about the structure of the regulator and corresponding filters. At least the DC loop gain and the position of the compensation zeros may be determined without requiring any prior knowledge of the values of the various components of the system. The compensator coefficients may be adjusted based on duty-cycle jitter information, which may be accurately obtained/measured at a high signal-to-noise ratio. By observing the duty-cycle jitter, the capacitor (equivalent series resistance) may be optimally compensated by tuning the 0 dB crossover slope of the loop gain. Accordingly, auto-compensation may be performed by measuring the duty-cycle jitter while maintaining optimum stability and transient performance.

72. 发明授权

US09728491B2 Systems and methods for lead frame locking design features 有权
公开(公告)号：US09728491B2
公开(公告)日：2017-08-08
申请号：US14829584
申请日：2015-08-18
申请人： INTERSIL AMERICAS LLC
发明人： Randolph Cruz
IPC分类号： H01L23/495 , H01L23/31 , H01L21/48
CPC分类号： H01L23/49548 , H01L21/4828 , H01L23/3107 , H01L23/3114 , H01L23/495 , H01L23/49503 , H01L23/49541 , H01L2224/32245
摘要： Systems and methods for lead frame locking design features are provided. In one embodiment, a method comprises: fabricating a lead frame for a chip package, the lead frame having a paddle comprising a step-out bottom locking feature profile across at least a first segment of an edge of the paddle that provides an interface with a mold compound; etching the paddle to have at least a second segment of the edge having either an extended-step-out bottom locking feature profile or an overhanging top locking feature profile; and alternating first and second segments along the edge of the paddle.

73. 发明授权

US09722490B2 Smooth transition of a power supply from a first mode, such as a pulse-frequency-modulation (PFM) mode, to a second mode, such as a pulse-width-modulation (PWM) mode 有权
公开(公告)号：US09722490B2
公开(公告)日：2017-08-01
申请号：US14231691
申请日：2014-03-31
申请人： Intersil Americas LLC
发明人： Nicholas Archibald
IPC分类号： H02M3/156 , G06F1/26 , H02M1/14 , H02M3/157 , H02M3/158 , H02M1/00
CPC分类号： H02M3/156 , G06F1/26 , H02M1/14 , H02M3/157 , H02M3/1588 , H02M2001/0025 , H02M2001/0032 , Y02B70/1466 , Y02B70/16
摘要： In an embodiment, an apparatus, such as a power-supply controller, includes a generator and an adjuster. The generator is configured to provide a switching signal that causes a power supply to generate a regulated output signal, and the adjuster is configured to impart a condition to the power supply while the power supply is operating in a first mode, the condition being approximately equal to a condition that the power supply would have if the power supply were operating in a second mode. For example, such an apparatus may be able to reduce or eliminate a transient on a regulated output signal (e.g., a regulated output voltage) when a power supply transitions from a first operating mode, such as a pulse-frequency-modulation (PFM) mode, to a second operating mode, such as a pulse-width-modulation (PWM) mode.

74. 发明申请

US20170207704A1 HYSTERETIC CURRENT MODE BUCK-BOOST CONTROL ARCHITECTURE 审中-公开
公开(公告)号：US20170207704A1
公开(公告)日：2017-07-20
申请号：US15474998
申请日：2017-03-30
申请人： Intersil Americas LLC
发明人： M. Jason HOUSTON , Eric M. SOLIE
IPC分类号： H02M3/158 , H02M1/08
摘要： A hysteretic current mode buck-boost voltage regulator including a buck-boost voltage converter, a switching controller, a window circuit, a ramp circuit, and a timing circuit. The timing circuit may be additional ramp circuits. The voltage converter is toggled between first and second switching states during a boost mode, is toggled between third and fourth switching states during a buck mode, and is sequentially cycled through each switching state during a buck-boost mode. The ramp circuit develops a ramp voltage that simulates current through the voltage converter, and switching is determined using the ramp voltage compared with window voltages provided by the window circuit. The window voltages establish frequency, and may be adjusted based on the input and output voltages. The timing circuit provides timing indications during the buck-boost mode to ensure that the second and fourth switching states have approximately the same duration to provide symmetry of the ramp signal.

75. 发明授权

US09671495B2 Systems and methods for optical proximity detection with multiple field of views 有权
公开(公告)号：US09671495B2
公开(公告)日：2017-06-06
申请号：US14521308
申请日：2014-10-22
申请人： Intersil Americas LLC
发明人： Manoj Bikumandla
IPC分类号： G01S17/02 , G01S17/46 , G01S7/486
CPC分类号： G01S17/026 , G01S7/4863 , G01S17/46
摘要： An optical proximity detector includes a plurality photodetectors (PDs) and a winner-take-all (WTA) circuit. Each of the PDs has a respective field of view (FOV) and produces a respective analog current detection signal indicative of light incident on and detected by the PD. In an embodiment, the WTA circuit includes a comparator and a multiplexor (MUX). The comparator compares the analog current detection signals produced by the PDs and produces a selection signal in dependence thereon. The MUX receives the analog current detection signals produced by the PDs and outputs one of the analog current detection signals in dependence on the selection signal produced by the comparator. Circuitry, which is shared by the PDs, produces a digital detection signal corresponding to the one of the analog current detection signals output by the MUX. Such design can be used to reduce power consumption, size and cost of an optical proximity detector.

76. 再颁专利

USRE46419E1 Active pulse positioning modulator 有权
公开(公告)号：USRE46419E1
公开(公告)日：2017-05-30
申请号：US14282756
申请日：2014-05-20
申请人： INTERSIL AMERICAS INC.
发明人： Robert H. Isham , Weihong Qiu
IPC分类号： G05F1/40
CPC分类号： H03K7/08 , H02M3/156 , H02M3/1584 , H03K7/04
摘要： An adaptive pulse positioning modulator including a sense circuit which provides a compensation signal indicative of output voltage error, a filter circuit having an input receiving the compensation signal and an output providing an adjust signal, a leading ramp circuit which provides a repetitive first leading edge ramp signal having a slope which is adjusted by the adjust signal, a comparator circuit which provides a first start trigger signal when the first leading edge ramp signal reaches the compensation signal and a first end trigger signal when a first trailing edge ramp signal reaches the compensation signal, a trailing ramp circuit which initiates ramping of the first trailing edge ramp signal when the first start trigger signal is provided, and a pulse control logic which asserts pulses on a PWM signal based on the trigger signals.

77. 发明授权

US09647558B2 System and method for maintaining a constant output voltage ripple in a buck converter in discontinuous conduction mode 有权
公开(公告)号：US09647558B2
公开(公告)日：2017-05-09
申请号：US14312678
申请日：2014-06-23
申请人： Intersil Americas, LLC
发明人： Michael Jason Houston , Steven Patrick Laur
IPC分类号： H02M3/158 , H02M1/15
CPC分类号： H02M3/157 , H02M1/083 , H02M1/15 , H02M3/158 , H02M3/1588 , Y02B70/1466
摘要： The system and method creates a substantially constant output voltage ripple in a buck converter in discontinuous conduction mode by varying the on-time of a pulse width modulator (PWM) signal driving the buck converter when the buck converter is operating in discontinuous conduction mode. A first signal is generated that is a function of the switching frequency of the buck converter. This signal is low-pass filtered and compared with a second signal that is a function of the switching frequency of the buck converter when operating in continuous conduction mode and with constant PWM on-time. The output signal generated by the comparator is a signal that is equal to the ratio of the first signal and the second signal. The on-time of a voltage controlled oscillator is controlled by the output signal, the oscillator signal causing the on-time of the PWM signal to vary in a controlled fashion.

78. 发明授权

US09503701B2 Scanning projectors that use guard bands to reduce color shifts, and methods and controllers for use therewith 有权
标题翻译：扫描使用保护带以减少颜色偏移的投影机，以及与其一起使用的方法和控制器
公开(公告)号：US09503701B2
公开(公告)日：2016-11-22
申请号：US14798259
申请日：2015-07-13
申请人： Intersil Americas LLC
发明人： Akihiro Asada
IPC分类号： H04N9/12 , H04N9/31
CPC分类号： H04N9/3182 , H04N9/3135 , H04N9/3164 , H04N9/3194
摘要： A scanning projector system includes a controller, a driver and one or more micro-mirror(s). The controller produces first, second and third pixel data in dependence on a video signal. The driver drives first, second and third light emitting elements in dependence on the first, second and third pixel data produced by the controller, to thereby emit light of first, second and third colors. The micro-mirror(s) project an image in dependence on light beams produced in dependence on the light of the first, second and third colors. To reduce color shifts due to inter-pixel interference, the controller and/or driver causes at least one timing guard band per pixel period associated with each instance of the pixel data.
摘要翻译：扫描投影仪系统包括控制器，驱动器和一个或多个微镜。控制器根据视频信号产生第一，第二和第三像素数据。驱动器根据由控制器产生的第一，第二和第三像素数据驱动第一，第二和第三发光元件，从而发射第一，第二和第三颜色的光。微镜根据根据第一，第二和第三颜色的光产生的光束投影图像。为了减少由于像素间干扰引起的颜色偏移，控制器和/或驱动器在与像素数据的每个实例相关联的每个像素周期引起至少一个定时保护带。

79. 发明申请

US20160306072A1 OPTOELECTRONIC DEVICE PACKAGES 审中-公开
标题翻译：光电器件封装
公开(公告)号：US20160306072A1
公开(公告)日：2016-10-20
申请号：US15055852
申请日：2016-02-29
申请人： Intersil Americas LLC
发明人： Sri Ganesh A Tharumalingam
IPC分类号： G01V8/12
CPC分类号： G01V8/12 , H01L24/94 , H01L24/97 , H01L25/167 , H01L31/167 , H01L31/186 , H01L2224/48091 , H01L2224/48145 , H01L2924/181 , H01L2924/00012 , H01L2924/00014
摘要： An optical proximity sensor comprises a light detector die including a light detector sensor area and at least one bond pad on a portion of the light detector die not including the light detector sensor area. A light source die, including anode and cathode terminals, is attached to a portion of the light detector die not including the light detector sensor area, such that at least one of the terminals of the light source die, on a bottom of the light source die, is attached to at least one of the bond pads on the light detector die. An opaque barrier, formed off-wafer relative to a wafer including the light detector die, is attached to and extends upward from a top surface of the light detector die between the light detector sensor area and the light source die. Electrical connectors are on the bottom of the light detector die.
摘要翻译：光学接近传感器包括光检测器管芯，其包括光检测器传感器区域和不包括光检测器传感器区域的光检测器管芯的一部分上的至少一个接合焊盘。包括阳极和阴极端子的光源管芯连接到不包括光检测器传感器区域的光检测器管芯的一部分，使得光源的至少一个端子在光源的底部模具附接到光检测器裸片上的至少一个接合焊盘。相对于包括光检测器裸片的晶片而在晶片外形成的不透明屏障附着到光检测器芯片的光表面和光源管芯之间并从光检测器管芯的上表面向上延伸。电连接器位于光检测器模具的底部。

80. 发明授权

US09383618B2 Semiconductor structures for enhanced transient response in low dropout (LDO) voltage regulators 有权
标题翻译：用于在低压差（LDO）稳压器中增强瞬态响应的半导体结构
公开(公告)号：US09383618B2
公开(公告)日：2016-07-05
申请号：US14336870
申请日：2014-07-21
申请人： INTERSIL AMERICAS LLC
发明人： Gwilym Luff
IPC分类号： G05F3/02 , G02F1/1368 , G05F1/56
CPC分类号： G02F1/1368 , G05F1/56 , G09G3/3696
摘要： Systems, semiconductor structures, electronic circuits and methods for enhanced transient response in Low Dropout (LDO) voltage regulators are disclosed. For example, a semiconductor structure for enhanced transient response in an LDO voltage regulator is disclosed, which includes a first current mirror circuit coupled to an input connection and an output connection of the LDO voltage regulator, a second current mirror circuit coupled to the input connection of the LDO voltage regulator. A first input of a first amplifier circuit is coupled to the second current mirror circuit, a second input of the first amplifier circuit is coupled to the output connection of the LDO voltage regulator, and a third input of the first amplifier circuit is coupled to a reference voltage. An input of a second amplifier circuit is coupled to an output of the first amplifier circuit, an output of the second amplifier circuit is coupled to the first current mirror circuit, an input of a third amplifier circuit is coupled to the output of the first amplifier circuit, and an output of the third amplifier circuit is coupled to the second current mirror circuit. In some implementations, the semiconductor structure is an adaptively-biased LDO voltage regulator formed in a power management integrated circuit (PMIC) or in a power supply on a semiconductor IC, wafer, chip or die.
摘要翻译：公开了用于增强低压差（LDO）稳压器中的瞬态响应的系统，半导体结构，电子电路和方法。例如，公开了一种用于LDO稳压器中的增强的瞬态响应的半导体结构，其包括耦合到LDO电压调节器的输入连接和输出连接的第一电流镜电路，耦合到输入连接的第二电流镜电路的LDO稳压器。第一放大器电路的第一输入耦合到第二电流镜电路，第一放大器电路的第二输入耦合到LDO电压调节器的输出连接，并且第一放大器电路的第三输入耦合到参考电压。第二放大器电路的输入耦合到第一放大器电路的输出，第二放大器电路的输出耦合到第一电流镜电路，第三放大器电路的输入耦合到第一放大器的输出端电路，并且第三放大器电路的输出耦合到第二电流镜电路。在一些实施方案中，半导体结构是形成在功率管理集成电路（PMIC）中或在半导体IC，晶片，芯片或管芯上的电源中形成的自适应偏置LDO电压调节器。

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