专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20130029488A1 Single Liner Process to Achieve Dual Stress 审中-公开
标题翻译：实现双重压力的单衬套工艺
公开(公告)号：US20130029488A1
公开(公告)日：2013-01-31
申请号：US13192744
申请日：2011-07-28
申请人： Ming Cai , Dechao Guo , Chun-chen Yeh
发明人： Ming Cai , Dechao Guo , Chun-chen Yeh
IPC分类号： H01L21/3205
CPC分类号： H01L21/28518 , H01L21/0217 , H01L21/3105 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L29/7843
摘要： Methods for imparting a dual stress property in a stress liner layer of a semiconductor device. The methods include depositing a metal layer over a compressive stress liner layer, applying a masking agent to a portion of the metal layer to produce a masked and unmasked region of the metal layer, etching the unmasked region of the metal layer to remove the metal layer in the unmasked region to thereby expose a corresponding portion of the compressive stress liner layer, removing the mask to expose the metal layer from the masked region, and irradiating the compressive stress liner layer to impart a tensile stress property to the exposed portion of the compressive stress liner layer. Methods are also provided for imparting a compressive-neutral dual stress property in a stress liner layer, as well as for imparting a neutral-tensile dual stress property in a stress liner layer.
摘要翻译：在半导体器件的应力衬垫层中赋予双重应力特性的方法。所述方法包括在压缩应力衬垫层上沉积金属层，向金属层的一部分施加掩蔽剂以产生金属层的掩蔽和未掩蔽区域，蚀刻金属层的未掩蔽区域以除去金属层在未掩蔽的区域中，从而暴露出压应力衬垫层的相应部分，去除掩模以使掩模区域露出金属层，并且照射压缩应力衬层以赋予压缩应力衬垫层的暴露部分的拉伸应力特性应力衬层。还提供了用于在应力衬垫层中赋予压缩中性双应力性质以及在应力衬垫层中赋予中性拉伸双应力性质的方法。

72. 发明申请

US20120299118A1 Multiple Threshold Voltages in Field Effect Transistor Devices 失效
标题翻译：场效应晶体管器件中的多个阈值电压
公开(公告)号：US20120299118A1
公开(公告)日：2012-11-29
申请号：US13560240
申请日：2012-07-27
申请人： Dechao Guo , Keith Kwong Hon Wong
发明人： Dechao Guo , Keith Kwong Hon Wong
IPC分类号： H01L27/088
CPC分类号： H01L29/78696 , H01L21/845 , H01L27/1211 , H01L29/42392 , H01L29/66795
摘要： A field effect transistor device includes a first conductive channel disposed on a substrate, a second conductive channel disposed on the substrate, a first gate stack formed on the first conductive channel, the first gate stack including a metallic layer having a first oxygen content, a second gate stack a formed on the second conductive channel, the second gate stack including a metallic layer having a second oxygen, an ion doped source region connected to the first conductive channel and the second conductive channel, and an ion doped drain region connected to the first conductive channel and the second conductive channel.
摘要翻译：场效应晶体管器件包括设置在衬底上的第一导电沟道，设置在衬底上的第二导电沟道，形成在第一导电沟道上的第一栅极叠层，第一栅叠层包括具有第一氧含量的金属层，形成在第二导电沟道上的第二栅极堆叠a，第二栅极堆叠包括具有第二氧的金属层，连接到第一导电沟道和第二导电沟道的离子掺杂源区，以及连接到第二导电沟的离子掺杂漏极区第一导电沟道和第二导电沟道。

73. 发明申请

US20120007181A1 Schottky FET Fabricated With Gate Last Process 失效
标题翻译：采用栅极末端工艺制造的肖特基FET
公开(公告)号：US20120007181A1
公开(公告)日：2012-01-12
申请号：US12834428
申请日：2010-07-12
申请人： Jin Cai , Dechao Guo , Marwan H. Khater , Christian Lavoie , Zhen Zhang
发明人： Jin Cai , Dechao Guo , Marwan H. Khater , Christian Lavoie , Zhen Zhang
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/665 , H01L29/66545 , H01L29/66621
摘要： A method for forming a field effect transistor (FET) includes forming a dummy gate on a top semiconductor layer of a semiconductor on insulator substrate; forming source and drain regions in the top semiconductor layer, wherein the source and drain regions are located in the top semiconductor layer on either side of the dummy gate; forming a supporting material over the source and drain regions adjacent to the dummy gate; removing the dummy gate to form a gate opening, wherein a channel region of the top semiconductor layer is exposed through the gate opening; thinning the channel region of the top semiconductor layer through the gate opening; and forming gate spacers and a gate in the gate opening over the thinned channel region.
摘要翻译：一种形成场效应晶体管（FET）的方法包括在绝缘体上半导体衬底的顶部半导体层上形成一个虚拟栅极; 在顶部半导体层中形成源极和漏极区域，其中源极和漏极区域位于虚拟栅极的任一侧的顶部半导体层中; 在与所述虚拟栅极相邻的所述源极和漏极区域上形成支撑材料; 去除所述伪栅极以形成栅极开口，其中所述顶部半导体层的沟道区域通过所述栅极开口暴露; 通过栅极开口来稀薄顶部半导体层的沟道区域; 以及在所述变薄的通道区域上的所述栅极开口中形成栅极间隔物和栅极。

74. 发明申请

US20110316565A1 SCHOTTKY JUNCTION SI NANOWIRE FIELD-EFFECT BIO-SENSOR/MOLECULE DETECTOR 有权
标题翻译：肖特基接头SI NANOWIRE现场效应生物传感器/分子检测器
公开(公告)号：US20110316565A1
公开(公告)日：2011-12-29
申请号：US12825527
申请日：2010-06-29
申请人： Dechao Guo , Christian Lavoie , Christine Qiqing Ouyang , Yanning Sun , Zhen Zhang
发明人： Dechao Guo , Christian Lavoie , Christine Qiqing Ouyang , Yanning Sun , Zhen Zhang
IPC分类号： G01R27/26 , H01L21/338 , H01L29/772 , H01L29/775
CPC分类号： G01N27/4145 , G01N27/4146 , H01L29/0673
摘要： A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecule of interest absorbs, which modulates the conductivity of the channel between the Schottky junctions sufficiently to qualitatively and quantitatively measure the presence and amount of the molecule.
摘要翻译：肖特基结的硅纳米线场效应生物传感器/分子检测器，纳米线厚度为10纳米或更小，并具有对准的源极/漏极功能，以提高灵敏度。纳米线通道涂覆有目标分子吸收的表面处理，其可以充分调节肖特基结之间的通道的电导率以定性和定量地测量分子的存在和量。

75. 发明申请

US20110248343A1 Schottky FET With All Metal Gate 审中-公开
标题翻译：所有金属门肖特基FET
公开(公告)号：US20110248343A1
公开(公告)日：2011-10-13
申请号：US12755720
申请日：2010-04-07
申请人： Dechao Guo , Marwan Khater , Christian Lavoie , Qiqing Ouyang , Zhen Zhang
发明人： Dechao Guo , Marwan Khater , Christian Lavoie , Qiqing Ouyang , Zhen Zhang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26513 , H01L21/265 , H01L21/28088 , H01L29/4966 , H01L29/66643 , H01L29/7839
摘要： A method for forming a Schottky field effect transistor (FET) includes forming a gate stack on a silicon substrate, the gate stack comprising a gate polysilicon on top of a gate metal layer; depositing a metal layer over the gate polysilicon and the silicon substrate; annealing the metal layer, the gate polysilicon, and the silicon substrate such that the metal layer fully consumes the gate polysilicon to form a gate silicide and reacts with portions of the silicon substrate to form source/drain silicide regions in the silicon substrate; and in the event a portion of the metal layer does not react with the gate polysilicon or the silicon substrate, removing the unreacted portion of the metal layer.
摘要翻译：一种用于形成肖特基场效应晶体管（FET）的方法包括在硅衬底上形成栅极堆叠，所述栅叠层在栅极金属层的顶部包括栅极多晶硅; 在栅极多晶硅和硅衬底上沉积金属层; 使金属层，栅极多晶硅和硅衬底退火，使得金属层完全消耗栅极多晶硅以形成栅极硅化物，并与硅衬底的部分反应以在硅衬底中形成源极/漏极硅化物区域; 并且在金属层的一部分不与栅极多晶硅或硅衬底反应的情况下，去除金属层的未反应部分。

76. 发明申请

US20110248321A1 Self-Aligned Contacts for Field Effect Transistor Devices 有权
标题翻译：场效应晶体管器件的自对准触点
公开(公告)号：US20110248321A1
公开(公告)日：2011-10-13
申请号：US12757201
申请日：2010-04-09
申请人： Dechao Guo , Wilfried E. Haensch , Xinhui Wang , Keith Kwong Hon Wong
发明人： Dechao Guo , Wilfried E. Haensch , Xinhui Wang , Keith Kwong Hon Wong
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/665 , H01L21/28088 , H01L21/28114 , H01L21/28525 , H01L21/76897 , H01L21/78 , H01L29/66545
摘要： A method for forming a field effect transistor includes forming a gate stack, a spacer adjacent to opposing sides of the gate stack, a silicide source region and a silicide drain region on opposing sides of the spacer, epitaxially growing silicon on the source region and the drain region; forming a liner layer on the gate stack and the spacer, removing a portion of the liner layer to expose a portion of the hardmask layer, removing the exposed portions of the hardmask layer to expose a silicon layer of the gate stack, removing exposed silicon to expose a portion of a metal layer of the gate stack, the source region, and the drain region; and depositing a conductive material on the metal layer of the gate stack, the silicide source region, and the silicide drain region.
摘要翻译：一种用于形成场效应晶体管的方法，包括：形成栅极叠层，与栅叠层的相对侧相邻的间隔物，在间隔物的相对侧上的硅化物源区和硅化物漏极区，在源区上外延生长硅，漏区; 在栅极堆叠和间隔物上形成衬垫层，去除衬里层的一部分以露出硬掩模层的一部分，去除硬掩模层的暴露部分以暴露栅堆叠的硅层，将暴露的硅去除暴露栅叠层，源极区和漏区的金属层的一部分; 以及在栅叠层，硅化物源区和硅化物漏极区的金属层上沉积导电材料。

77. 发明申请

US20110095379A1 SCALING OF METAL GATE WITH ALUMINUM CONTAINING METAL LAYER FOR THRESHOLD VOLTAGE SHIFT 审中-公开
标题翻译：金属门与铝包含金属层用于阈值电压转换
公开(公告)号：US20110095379A1
公开(公告)日：2011-04-28
申请号：US12607110
申请日：2009-10-28
申请人： Keith Kwong Hon Wong , Dechao Guo , Unoh Kwon
发明人： Keith Kwong Hon Wong , Dechao Guo , Unoh Kwon
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/511 , H01L21/28079 , H01L21/28088 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.
摘要翻译：提供一种形成p型半导体器件的方法，其在一个实施例中使用含铝的阈值电压移位层，以产生朝向p型半导体器件的价带的阈值电压偏移。形成p型半导体器件的方法可以包括在衬底上形成栅极结构，其中栅极结构包括与衬底接触的栅极电介质层，存在于栅极电介质层上的含铝的阈值电压移位层，以及与含铝的阈值电压移位层和栅极电介质层中的至少一个接触的含金属层。 P型源极和漏极区可以形成在衬底附近，栅极结构所在的衬底的相邻部分。还提供了通过上述方法提供的p型半导体器件。

78. 发明申请

US20110012629A1 REPLACEMENT-GATE-COMPATIBLE PROGRAMMABLE ELECTRICAL ANTIFUSE 有权
标题翻译：替代可控可编程电抗器
公开(公告)号：US20110012629A1
公开(公告)日：2011-01-20
申请号：US12503116
申请日：2009-07-15
申请人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Rajeevakumar V. Thekkemadathil , Keith Kwong Hon Wong
发明人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Rajeevakumar V. Thekkemadathil , Keith Kwong Hon Wong
IPC分类号： G01R27/08 , H01L27/06 , H01L21/28 , H01H37/76
CPC分类号： H01L27/0617 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L29/4966 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).
摘要翻译：在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。第一导电材料层和无定形金属氧化物沉积到凹陷区域中。第二导电材料层填充凹部。在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。为了编程电反熔丝，电流在一对导电触头中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。

79. 发明授权

US09437677B2 Deposition on a nanowire using atomic layer deposition 有权
标题翻译：使用原子层沉积在纳米线上沉积
公开(公告)号：US09437677B2
公开(公告)日：2016-09-06
申请号：US13604739
申请日：2012-09-06
申请人： Dechao Guo , Zhengwen Li , Kejia Wang , Zhen Zhang , Yu Zhu
发明人： Dechao Guo , Zhengwen Li , Kejia Wang , Zhen Zhang , Yu Zhu
IPC分类号： H01L29/775 , B82Y99/00 , H01L29/06 , H01L21/84 , H01L27/12 , H01L29/47 , H01L29/66 , H01L29/78 , B82Y30/00 , B82Y40/00 , B82Y10/00 , H01L51/00 , H01L51/05
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/84 , H01L21/845 , H01L27/1203 , H01L27/1211 , H01L29/42392 , H01L29/47 , H01L29/6675 , H01L29/7839 , H01L51/0048 , H01L51/0516 , H01L51/0558 , H01L51/057 , Y10S977/762 , Y10S977/938
摘要： A semiconductor device includes a substrate, a nanowire, a first structure, and a second structure. The nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate, where the nanowire includes a layer on a surface of the nanowire, where the layer includes at least one of silicide and carbide, where the layer has a substantially uniform shape.
摘要翻译：半导体器件包括衬底，纳米线，第一结构和第二结构。纳米线悬挂在第一结构和第二结构之间，其中第一结构和第二结构超过衬底，其中纳米线包括纳米线表面上的层，其中该层包括硅化物和碳化物中的至少一种，其中该层具有基本均匀的形状。

80. 发明授权

US09059006B2 Replacement-gate-compatible programmable electrical antifuse 有权
标题翻译：替换门兼容可编程电气反熔丝
公开(公告)号：US09059006B2
公开(公告)日：2015-06-16
申请号：US13523120
申请日：2012-06-14
申请人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Thekkemadathil V. Rajeevakumar , Keith Kwong Hon Wong
发明人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Thekkemadathil V. Rajeevakumar , Keith Kwong Hon Wong
IPC分类号： G01R27/08 , H01L23/52 , H01L29/10 , H01L27/06 , H01L23/525 , H01L27/112 , H01L29/66 , H01L29/49 , H01L29/78
CPC分类号： H01L27/0617 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L29/4966 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).
摘要翻译：在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。第一导电材料层和无定形金属氧化物沉积到凹陷区域中。第二导电材料层填充凹部。在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。为了编程电反熔丝，电流在一对导电触点中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式