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71. 发明授权

US08486803B2 Wafer level packaging method of encapsulating the bottom and side of a semiconductor chip 有权
标题翻译：封装半导体芯片的底部和侧面的晶片级封装方法
公开(公告)号：US08486803B2
公开(公告)日：2013-07-16
申请号：US13273168
申请日：2011-10-13
申请人： Ping Huang , Ruisheng Wu , Lei Duan , Yi Chen , Yuping Gong
发明人： Ping Huang , Ruisheng Wu , Lei Duan , Yi Chen , Yuping Gong
IPC分类号： H01L21/30
CPC分类号： H01L23/3171 , H01L21/568 , H01L23/3114 , H01L24/19 , H01L24/96 , H01L2224/02379 , H01L2224/12105 , H01L2924/1306 , H01L2924/13091 , H01L2924/15788 , H01L2924/181 , H01L2924/18162 , H01L2924/00
摘要： A chip-scale packaging method, with bottom and side of a semiconductor chip encapsulated, includes the following steps: attaching backside of a thinned semiconductor wafer to a dicing tape; separating individual chips by cutting from front side of the wafer at scribe line but not cut through the dicing tape; flipping and attaching the wafer onto a top surface of a double-sided tape, then removing the dicing tape; attaching bottom surface of the double-sided tape on a supporting plate; filling the space between adjacent chips and covering the whole wafer backside with a molding material; flipping the whole structure and remove the supporting plate; placing solder balls at corresponding positions on electrodes of each chip and performing backflow treatment; finally separating individual chip packages by cutting through molding material at the space between adjacent chip packages with molding material encapsulating the bottom and side of each individual semiconductor chip.
摘要翻译：封装了半导体芯片的底部和侧面的芯片级封装方法包括以下步骤：将薄化的半导体晶片的背面安装到切割带上; 通过在切割线处切割晶片的正面而不切割切割带来分离各个芯片; 翻转并将晶片连接到双面胶带的顶表面上，然后移除切割胶带; 将双面胶带的底面附着在支撑板上; 填充相邻芯片之间的空间并用模制材料覆盖整个晶片背面; 翻转整个结构并拆下支撑板; 将焊球放置在每个芯片的电极上的相应位置，并执行回流处理; 最后通过在封装每个单独的半导体芯片的底部和侧面的成型材料之间切割相邻芯片封装之间的空间处的模制材料来分离单个芯片封装。

72. 发明授权

US08439994B2 Method of fabricating a polishing pad with an end-point detection region for eddy current end-point detection 有权
标题翻译：制造具有用于涡流端点检测的端点检测区域的抛光垫的方法
公开(公告)号：US08439994B2
公开(公告)日：2013-05-14
申请号：US12895529
申请日：2010-09-30
申请人： William C. Allison , Diane Scott , Ping Huang , Richard Frentzel , Alexander William Simpson
发明人： William C. Allison , Diane Scott , Ping Huang , Richard Frentzel , Alexander William Simpson
IPC分类号： B24D11/00 , B24D3/00 , B24D18/00
CPC分类号： B24B37/205 , B24B37/26 , B24D18/0009
摘要： Methods of fabricating polishing pads with end-point detection regions for polishing semiconductor substrates using eddy current end-point detection are described.
摘要翻译：描述了使用涡流端点检测来制造用于抛光半导体衬底的端点检测区域的抛光垫的方法。

73. 外观设计

USD681795S1 Fan 有权
公开(公告)号：USD681795S1
公开(公告)日：2013-05-07
申请号：US29431101
申请日：2012-09-04
申请人： Ping Huang
设计人： Ping Huang

74. 发明授权

US08324231B2 Pyrimidinones as casein kinase II (CK2) modulators 失效
标题翻译：嘧啶酮作为酪蛋白激酶II（CK2）调节剂
公开(公告)号：US08324231B2
公开(公告)日：2012-12-04
申请号：US12597271
申请日：2008-04-24
申请人： Elena S. Koltun , Patrick Kearney , Naing Aay , Arlyn Arcalas , Wai Ki Vicky Chan , Jeffry Kimo Curtis , Hongwang Du , Ping Huang , Brian Kane , Moon Hwan Kim , Michael Pack , Amy L. Tsuhako , Wei Xu , Cristiana A. Zaharia , Peiwen Zhou
发明人： Elena S. Koltun , Patrick Kearney , Naing Aay , Arlyn Arcalas , Wai Ki Vicky Chan , Jeffry Kimo Curtis , Hongwang Du , Ping Huang , Brian Kane , Moon Hwan Kim , Michael Pack , Amy L. Tsuhako , Wei Xu , Cristiana A. Zaharia , Peiwen Zhou
IPC分类号： A01N43/54 , A61K31/505
CPC分类号： C07D405/04 , C07D403/04 , C07D413/04 , C07D417/04
摘要： A compound having Formula I: or a pharmaceutically acceptable salt thereof, wherein X, R, R and R are as defined in the specification; pharmaceutical compositions thereof; and methods of use thereof. The compounds of Formula I are inhibitors of Casein kinase II (CK2) pathways.
摘要翻译：具有式I的化合物或其药学上可接受的盐，其中X，R，R和R如说明书中所定义; 其药物组合物; 及其使用方法。式I的化合物是酪蛋白激酶II（CK2）途径的抑制剂。

75. 外观设计

USD664248S1 Vertically-oriented air purifying and humidifying apparatus 有权
标题翻译：垂直取向的空气净化和加湿装置
公开(公告)号：USD664248S1
公开(公告)日：2012-07-24
申请号：US29412566
申请日：2012-02-06
申请人： Ping Huang , Ying-Pin Huang , Chia-Chang Lee
设计人： Ping Huang , Ying-Pin Huang , Chia-Chang Lee

76. 发明授权

US08163771B2 11 β-HSD1 modulators 失效
标题翻译： 11＆bgr; -HSD1调节剂
公开(公告)号：US08163771B2
公开(公告)日：2012-04-24
申请号：US12381682
申请日：2009-03-13
申请人： Richard Martin , Brenton T. Flatt , Jackline Eve Dalgard , Venkataiah Bollu , Ping Huang , Raju Mohan , Edwin Schweiger , Tie-Lin Wang
发明人： Richard Martin , Brenton T. Flatt , Jackline Eve Dalgard , Venkataiah Bollu , Ping Huang , Raju Mohan , Edwin Schweiger , Tie-Lin Wang
IPC分类号： A10N43/42 , A61K31/44 , C07D451/00
CPC分类号： C07D451/04
摘要： A compound according to Formula I: or a pharmaceutically acceptable salt thereof, wherein R1, R2, R11, L1 and X are as defined in the specification, pharmaceutical compositions thereof, and methods of use thereof.
摘要翻译：根据式I的化合物或其药学上可接受的盐，其中R 1，R 2，R 11，L 1和X如本说明书中所定义，其药物组合物及其使用方法。

77. 发明申请

US20120079773A1 METHOD OF FABRICATING A POLISHING PAD WITH AN END-POINT DETECTION REGION FOR EDDY CURRENT END-POINT DETECTION 有权
标题翻译：用于EDDY电流端点检测的具有端点检测区域的抛光垫的制造方法
公开(公告)号：US20120079773A1
公开(公告)日：2012-04-05
申请号：US12895529
申请日：2010-09-30
申请人： William C. Allison , Diane Scott , Ping Huang , Richard Frentzel , Alexander William Simpson
发明人： William C. Allison , Diane Scott , Ping Huang , Richard Frentzel , Alexander William Simpson
IPC分类号： B24D3/20 , B24D18/00
CPC分类号： B24B37/205 , B24B37/26 , B24D18/0009
摘要： Methods of fabricating polishing pads with end-point detection regions for polishing semiconductor substrates using eddy current end-point detection are described.
摘要翻译：描述了使用涡流端点检测来制造用于抛光半导体衬底的端点检测区域的抛光垫的方法。

78. 发明申请

US20120075006A1 ZERO PIN SERIAL INTERFACE 有权
公开(公告)号：US20120075006A1
公开(公告)日：2012-03-29
申请号：US13075617
申请日：2011-03-30
申请人： Hoa Vu , Ping Huang
发明人： Hoa Vu , Ping Huang
IPC分类号： H01H37/76
CPC分类号： G01R31/2884
摘要： A method for controlling performance of an integrated circuit using a zero-pin serial interface is provided. The method comprises identifying a desired performance characteristic of the circuit, and transmitting a first change mode signal to the circuit on a first pin to cause the circuit to enter an instruction reception mode, with the first pin performing differently during a normal operation mode. The method also comprises transmitting a performance adjusting instruction to the circuit on a second pin when the circuit is in the instruction reception mode, with the second pin performing differently during the normal operation mode, and transmitting a second change mode signal to the circuit on the first pin to cause the circuit to enter the normal operation mode. An output performance of the circuit is compared to the desired performance characteristic, with the output performance being the performance of the circuit during the normal operation mode. The circuit is set to permanently provide the output performance when the output performance is within a desired tolerance of the desired performance characteristic.
摘要翻译：提供了一种使用零引脚串行接口来控制集成电路的性能的方法。该方法包括识别电路的期望性能特征，以及在第一引脚上向第一引脚上的电路发送第一改变模式信号以使电路进入指令接收模式，其中第一引脚在正常操作模式期间执行不同的操作。该方法还包括当电路处于指令接收模式时，向第二引脚上的电路发送性能调整指令，其中第二引脚在正常操作模式期间执行不同的操作，并且向第二引脚上的电路发送第二改变模式信号第一个引脚使电路进入正常工作模式。将电路的输出性能与期望的性能特性进行比较，输出性能是正常操作模式期间电路的性能。当输出性能在期望的性能特性的期望公差内时，电路被设置为永久地提供输出性能。

79. 发明申请

US20100327314A1 Insulated Gate Bipolar Transistor (IGBT) Collector Formed with Ge/A1 and Production Method 审中-公开
标题翻译：绝缘栅双极晶体管（IGBT）采用Ge / A1及其制作方法
公开(公告)号：US20100327314A1
公开(公告)日：2010-12-30
申请号：US12493226
申请日：2009-06-28
申请人： Ping Huang , Tao Feng , Ruisheng Wu , Yi Chen , Lei Duan
发明人： Ping Huang , Tao Feng , Ruisheng Wu , Yi Chen , Lei Duan
IPC分类号： H01L29/739 , H01L21/20
CPC分类号： H01L29/7395 , H01L29/0834 , H01L29/165 , H01L29/66333
摘要： This invention discloses an IGBT device with its collector formed with Ge/Al and associated method of fabrication. The collector is formed on the substrate layer, which is on the back of IGBT, and contains Ge and Al thin films. After thinning and etching the back side of IGBT substrate, Ge and Al are sequentially deposited to form Ge/Al thin films on the back surface of the substrate. An annealing process is then carried out to diffuse Al into Ge thin film layer to form a P-doped Ge layer functioning as the IGBT collector. The present invention is applicable to both non punch through IGBTs as well as punch through IGBTs.
摘要翻译：本发明公开了一种IGBT器件，其集电极形成Ge / Al及其制造方法。集电体形成在IGBT背面的基板层上，并含有Ge和Al薄膜。在对IGBT基板的背面进行变薄蚀刻之后，依次沉积Ge和Al，以在衬底的背面形成Ge / Al薄膜。然后进行退火处理以将Al扩散到Ge薄膜层中，以形成用作IGBT集电极的P掺杂Ge层。本发明适用于非穿通IGBT以及穿通IGBT。

80. 发明申请

US20100135954A1 6-Phenylpyrimidinones as PIM Modulators 失效
标题翻译： 6-苯基嘧啶酮作为PIM调制剂
公开(公告)号：US20100135954A1
公开(公告)日：2010-06-03
申请号：US12597275
申请日：2008-04-25
申请人： Amy L. Tsuhako , Naing Aay , S. David Brown , Wai Ki Vicky Chan , Hongwang Du , Ping Huang , Brian Kane , Patrick Kearney , Moon Hwan Kim , Elena S. Koltun , Michael Pack , Wei Xu , Peiwen Zhou
发明人： Amy L. Tsuhako , Naing Aay , S. David Brown , Wai Ki Vicky Chan , Hongwang Du , Ping Huang , Brian Kane , Patrick Kearney , Moon Hwan Kim , Elena S. Koltun , Michael Pack , Wei Xu , Peiwen Zhou
IPC分类号： A61K38/20 , A61K38/21 , A61K31/567 , A61K31/5377 , A61K31/496 , A61K31/506 , C07D413/02 , C07D403/10 , C07D401/10 , A61P35/00
CPC分类号： C07D213/64 , C07D239/36 , C07D401/12 , C07D403/12 , C07D405/12 , C07D407/12 , C07D409/04 , C07D409/12 , C07D413/04
摘要： A compound having Formula I or II (Formula I) or (Formula II), or a pharmaceutically acceptable salt thereof, wherein X, Z, R1, R2, R11 and R12 are as defined in the specification; pharmaceutical compositions thereof; and methods of use thereof.
摘要翻译：具有式I或II（式I）或（式II）的化合物或其药学上可接受的盐，其中X，Z，R 1，R 2，R 11和R 12如说明书中所定义; 其药物组合物; 及其使用方法。

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