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71. 发明申请

US20070124797A1 Policy based service management 有权
标题翻译：基于策略的服务管理
公开(公告)号：US20070124797A1
公开(公告)日：2007-05-31
申请号：US10866508
申请日：2004-06-12
申请人： Rajiv Gupta , Sekhar Sarukkai
发明人： Rajiv Gupta , Sekhar Sarukkai
IPC分类号： H04L9/00
CPC分类号： H04L63/102 , H04L67/02 , H04L67/28 , H04L67/2823
摘要： A system and a method for policy management in a web services environment includes a policy design tool, a policy storage and a policy manager controller. The policy design tool creates (or updates) a policy for association with a web service. The policy storage stores the policy. The policy manager controller provides an interface for transmission of the policy to a policy enforcement tool and also receives messages relating to the policy from the policy enforcement tool. In addition, a system and method for policy enforcement in a web services environment includes a policy enforcement controller, a policy enforcement repository, an enforcer, a policy enforcement framework, and a policy container. The policy enforcement controller receives and commits a policy and the policy enforcement repository stores the committed policy. The enforcer module receives a request to invoke the policy and the policy enforcement framework determines whether the requested policy is committed in the policy enforcement repository and whether the policy is instantiated. The policy container determines whether the policy is enforceable.
摘要翻译：用于Web服务环境中的策略管理的系统和方法包括策略设计工具，策略存储和策略管理器控制器。策略设计工具创建（或更新）与Web服务关联的策略。策略存储存储策略。策略管理器控制器提供用于将策略传输到策略执行工具的接口，并且还从策略执行工具接收与该策略相关的消息。另外，用于web服务环境中的策略执行的系统和方法包括策略执行控制器，策略实施库，执行器，策略实施框架和策略容器。策略执行控制器接收并提交策略，策略执行库存储所承诺的策略。执行者模块接收到调用策略的请求，策略执行框架确定策略执行库中是否提交了请求的策略，以及策略是否被实例化。策略容器确定策略是否可执行。

72. 发明授权

US07191430B2 Providing instruction execution hints to a processor using break instructions 失效
标题翻译：使用break指令向处理器提供指令执行提示
公开(公告)号：US07191430B2
公开(公告)日：2007-03-13
申请号：US09963270
申请日：2001-09-24
申请人： Alan H. Karp , Rajiv Gupta
发明人： Alan H. Karp , Rajiv Gupta
IPC分类号： G06F9/44
CPC分类号： G06F9/3005 , G06F8/52 , G06F9/30047 , G06F9/322 , G06F9/328 , G06F9/383 , G06F9/3846
摘要： A computer system with mechanisms for providing hint instructions to a processor without altering object code instruction sequences. A computer system according to the present teachings includes elements for generating a hint instruction in response to a set of object code to be executed by the processor and for inserting a break instruction into the object code such that the break instruction causes the processor to obtain and execute the hint instruction. The present techniques for providing hint instructions to a processor may be used to adapt object code to a micro-architecture of the processor.
摘要翻译：一种具有用于向处理器提供提示指令而不改变目标代码指令序列的机制的计算机系统。根据本教导的计算机系统包括用于响应于要由处理器执行的一组目标代码产生提示指令并用于将中断指令插入到目标代码中的元件，使得中断指令导致处理器获得和执行提示说明。用于向处理器提供提示指令的现有技术可以用于将目标代码适配到处理器的微架构。

73. 发明授权

US06883516B2 Method for generating an aerosol with a predetermined and/or substantially monodispersed particle size distribution 有权
标题翻译：用于产生具有预定和/或基本上单分散的粒度分布的气溶胶的方法
公开(公告)号：US06883516B2
公开(公告)日：2005-04-26
申请号：US09981739
申请日：2001-10-19
申请人： Michael Hindle , Peter R. Byron , Rajiv Gupta
发明人： Michael Hindle , Peter R. Byron , Rajiv Gupta
IPC分类号： A61K9/72 , A61K9/00 , A61K9/12 , A61K31/573 , A61K31/58 , A61K47/10 , A61M5/00 , A61M11/00 , A61M11/04 , A61M15/00 , A61M16/00 , A61M16/10 , A61P11/00 , B67D7/80
CPC分类号： A61K9/007 , A61K9/0073 , A61M11/007 , A61M11/041 , A61M11/042 , A61M16/109 , A61M2016/0024 , A61M2205/8206
摘要： A method is provided for generating an aerosol. The method includes preparing a solution formed of a first component in a liquid component such that after volatilization of the liquid component by passing the solution through a flow passage while heating the solution, an aerosol is formed having a predetermined particle size distribution of the first component, wherein the solution is prepared such that the amount of the first component therein is sufficient to achieve the predetermined particle size distribution of the first component. The method also includes passing the solution through the flow passage while heating the solution to a temperature sufficient to volatilize the liquid component, wherein the flow passage comprises an outlet through which the first component and the volatilized liquid component flow, and wherein an aerosol is formed.
摘要翻译：提供了一种产生气溶胶的方法。该方法包括制备由液体组分中的第一组分形成的溶液，使得在加热溶液的同时通过使溶液通过流动通道使液体组分挥发，形成具有预定的第一组分的粒度分布的气溶胶其中制备溶液使得其中的第一组分的量足以实现第一组分的预定的粒度分布。该方法还包括使溶液通过流动通道，同时将溶液加热到足以挥发液体组分的温度，其中流动通道包括第一组分和挥发的液体组分流过的出口，并且其中形成气溶胶。

74. 发明申请

US20050066153A1 Method for processing branch operations 审中-公开
标题翻译：处理分支操作的方法
公开(公告)号：US20050066153A1
公开(公告)日：2005-03-24
申请号：US10461782
申请日：2003-06-12
申请人： Harshvardhan Sharangpani , Tse-Yu Yeh , Michael Paul Corwin , Millind Mittal , Kent Fielden , Dale Morris , Rajiv Gupta , Michael Schlansker , Mircea Poplingher
发明人： Harshvardhan Sharangpani , Tse-Yu Yeh , Michael Paul Corwin , Millind Mittal , Kent Fielden , Dale Morris , Rajiv Gupta , Michael Schlansker , Mircea Poplingher
IPC分类号： G06F9/32 , G06F9/38 , G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/325 , G06F9/3844 , G06F9/3846
摘要： A branch operation is processed using a branch predict instruction and an associated branch instruction. The branch predict instruction indicates a predicted direction, a target address, and an instruction address for the associated branch instruction. When the branch predict instruction is detected, the target address is stored at an entry indicated by the associated branch instruction address and a prefetch request is triggered to the target address. The branch predict instruction may also include hint information for managing the storage and use of the branch prediction information.
摘要翻译：使用分支预测指令和相关联的分支指令来处理分支操作。分支预测指示指示相关联的分支指令的预测方向，目标地址和指令地址。当检测到分支预测指令时，目标地址被存储在由关联的分支指令地址指示的条目上，并且预取请求被触发到目标地址。分支预测指令还可以包括用于管理分支预测信息的存储和使用的提示信息。

75. 发明授权

US06493712B1 Self-describing attribute vocabularies in a software system 失效
标题翻译：自我描述属性词汇在软件系统中
公开(公告)号：US06493712B1
公开(公告)日：2002-12-10
申请号：US09376149
申请日：1999-08-17
申请人： Alan H. Karp , Rajiv Gupta , Arindam Banerji , Chia-Chiang Chao , Ernest Mak , Sandeep Kumar
发明人： Alan H. Karp , Rajiv Gupta , Arindam Banerji , Chia-Chiang Chao , Ernest Mak , Sandeep Kumar
IPC分类号： G06F1730
CPC分类号： H04L29/12113 , H04L29/06 , H04L61/1541 , H04L67/16 , H04L69/329 , Y10S707/99936 , Y10S707/99943
摘要： A software system with self-describing attribute vocabularies that enhance the capability of service providers to advertise their resources and that facilitate the addition of new types of attributes and resources to the system. Each self-describing attribute vocabulary is characterized by a corresponding set of attribute properties and a corresponding set of:matching rules that are adapted to the corresponding attribute properties. The software system includes a matching engine that enables a service provider of a resource to describe the resource to the software system in terms of any one or more of the self-describing attribute vocabularies.
摘要翻译：具有自描述属性词汇的软件系统，其增强服务提供商宣传其资源的能力，并且促进向系统添加新类型的属性和资源。每个自描述属性词汇表都具有相应的一组属性属性和相应的一组：适应于相应属性属性的匹配规则。软件系统包括匹配的引擎，使得资源的服务提供者能够根据任何一个或多个自描述属性词汇表将资源描述给软件系统。

76. 发明授权

US06205519B1 Cache management for a multi-threaded processor 失效
标题翻译：多线程处理器的缓存管理
公开(公告)号：US06205519B1
公开(公告)日：2001-03-20
申请号：US09085644
申请日：1998-05-27
申请人： Robert Aglietti , Rajiv Gupta
发明人： Robert Aglietti , Rajiv Gupta
IPC分类号： G06F1200
CPC分类号： G06F12/0842 , G06F12/0864 , G06F12/0895 , G06F12/128
摘要： A method and apparatus which provides a cache management policy for use with a cache memory for a multi-threaded processor. The cache memory is partitioned among a set of threads of the multi-threaded processor. When a cache miss occurs, a replacement line is selected in a partition of the cache memory which is allocated to the particular thread from which the access causing the cache miss originated, thereby preventing pollution to partitions belonging to other threads.
摘要翻译：一种提供与多线程处理器的高速缓冲存储器一起使用的高速缓存管理策略的方法和装置。高速缓冲存储器在多线程处理器的一组线程之间分区。当发生高速缓存未命中时，在分配给导致高速缓存未命中的访问的特定线程的高速缓冲存储器的分区中选择替换行，从而防止对属于其他线程的分区的污染。

77. 发明授权

US5802374A Synchronizing parallel processors using barriers extending over specific multiple-instruction regions in each instruction stream 失效
标题翻译：使用在每个指令流中的特定多指令区域上延伸的障碍来同步并行处理器
公开(公告)号：US5802374A
公开(公告)日：1998-09-01
申请号：US839731
申请日：1997-04-15
申请人： Rajiv Gupta , Michael Abraham Epstein
发明人： Rajiv Gupta , Michael Abraham Epstein
IPC分类号： G06F15/16 , G06F9/45 , G06F9/46 , G06F9/52 , G06F15/177 , G06F15/80 , G06F9/44
CPC分类号： G06F9/3834 , G06F8/458 , G06F9/30087
摘要： A barrier is used to synchronize parallel processors. The barrier is "fuzzy", i.e. it includes several instructions in each instruction stream. None of the processors performing related tasks can execute an instruction after its respective fuzzy barrier until the others have finished the instruction immediately preceding their respective fuzzy barriers. Processors therefore spend less time waiting for each other. A state machine is used to keep track of synchronization states during the synchronization process.
摘要翻译：使用屏障来同步并行处理器。屏障是“模糊的”，即它包括每个指令流中的几个指令。执行相关任务的处理器中的任何一个都不能在其各自的模糊屏障之后执行指令，直到其他人已经完成在它们各自的模糊屏障之前的指令。因此，处理器花费更少的时间等待对方。状态机用于在同步过程中跟踪同步状态。

78. 发明授权

US5801977A System and method for clipping integers 失效
标题翻译：用于剪切整数的系统和方法
公开(公告)号：US5801977A
公开(公告)日：1998-09-01
申请号：US826817
申请日：1997-04-07
申请人： Alan H. Karp , Dennis Brzezinski , Rajiv Gupta
发明人： Alan H. Karp , Dennis Brzezinski , Rajiv Gupta
IPC分类号： G06F7/00 , G06F7/76 , G06F9/30 , G06F9/302 , G06F7/38
CPC分类号： G06F7/764 , G06F9/30014 , G06F9/30036
摘要： A circuit and method for clipping input integers to a specified range comprising the steps of providing a mask wherein a bit is set for each out-of-range bit and not set for in-range bits and applying the mask to input integers so that any integers outside of the range is clipped to the quantity in the range closest to the integer, thereby producing output integers within a range specified by the mask. Other systems and methods are disclosed.
摘要翻译：一种用于将输入整数剪切到指定范围的电路和方法，包括以下步骤：提供掩模，其中为每个超范围位设置位，并且不为范围内位设置位，并将掩码应用于输入整数，使得任何超出范围的整数被剪裁到最接近整数的范围内的数量，从而在掩码指定的范围内产生输出整数。公开了其它系统和方法。

79. 发明授权

US5689653A Vector memory operations 失效
标题翻译：矢量内存操作
公开(公告)号：US5689653A
公开(公告)日：1997-11-18
申请号：US384308
申请日：1995-02-06
申请人： Alan H. Karp , Frederic C. Amerson , Dennis Brzezinski , Rajiv Gupta , William S. Worley, Jr.
发明人： Alan H. Karp , Frederic C. Amerson , Dennis Brzezinski , Rajiv Gupta , William S. Worley, Jr.
IPC分类号： G06F9/312 , G06F9/345 , G06F9/38 , G06F12/00 , G06F15/78 , G06F17/16 , G06F9/00 , G06F13/00
CPC分类号： G06F9/30043 , G06F15/8084 , G06F9/30036 , G06F9/3455 , G06F9/383
摘要： The op-code bandwidth limitation of computer systems is alleviated by providing one or more vector buffers. Data is transferred between memory and processor registers in a two part process using the vector buffers. In a first part, a vector request instruction initiates buffering of data by storing data in control registers identifying a set of data elements (a vector) in the memory. When the identifying information is loaded in the control registers, a vector prefetch controller transfers elements of the vector between the memory and a vector buffer. In a second part, vector element operation instructions transfer a next element of the vector between the vector buffer and a specified processor register for use in arithmetic or logic operations.
摘要翻译：通过提供一个或多个向量缓冲器来减轻计算机系统的操作码带宽限制。数据在存储器和处理器寄存器之间使用向量缓冲区在两部分进程中传输。在第一部分中，向量请求指令通过将数据存储在识别存储器中的一组数据元素（矢量）的控制寄存器中来发起数据的缓冲。当识别信息被加载到控制寄存器中时，向量预取控制器在存储器和向量缓冲器之间传送向量的元素。在第二部分中，向量元素操作指令将矢量的下一个元素传送到矢量缓冲器和指定的处理器寄存器之间，用于算术或逻辑运算。

80. 发明授权

US5615386A Computer architecture for reducing delays due to branch instructions 失效
标题翻译：用于减少分支指令导致的延迟的计算机体系结构
公开(公告)号：US5615386A
公开(公告)日：1997-03-25
申请号：US588151
申请日：1996-01-18
申请人： Frederic C. Amerson , Rajiv Gupta , Balasubramanian Kumar , Michael S. Schlansker , William S. Worley
发明人： Frederic C. Amerson , Rajiv Gupta , Balasubramanian Kumar , Michael S. Schlansker , William S. Worley
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/3844
摘要： An improved data processing system for executing branch instructions which has lower latency times and which only rarely requires the instruction pipeline to be flushed is disclosed. The data processing system utilizes a register file to hold the information needed to execute a branch instruction. The information is loaded into the register file in advance of the branch instruction. This allows the system to prepare more than one branch instruction at any given time. The present invention may be used to cause the cache line containing the target address of the branch instruction to be loaded soon as the target address is available for the branch instruction. Since the outcome of the branch instruction is almost always known when the branch instruction enters the instruction pipeline, the instruction pipeline only rarely needs to be flushed.
摘要翻译：公开了一种用于执行具有较低等待时间并且很少需要刷新指令流水线的分支指令的改进的数据处理系统。数据处理系统利用寄存器文件来保存执行分支指令所需的信息。信息在分支指令之前被加载到寄存器文件中。这允许系统在任何给定时间准备多个分支指令。本发明可以用于使得包含分支指令的目标地址的高速缓存线在目标地址对于分支指令可用时很快被加载。由于分支指令的结果在分支指令进入指令流水线时几乎总是被知道，所以指令流水线很少需要刷新。

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