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    • 72. 发明申请
    • Sample and hold circuit based on an ultra linear switch
    • 基于超线性开关的采样和保持电路
    • US20050057283A1
    • 2005-03-17
    • US10927416
    • 2004-08-27
    • Sumant Ranganathan
    • Sumant Ranganathan
    • G11C27/02H03K5/00H03K17/06H03K17/687H03K17/693
    • H03K17/063G11C27/02H03K17/6872H03K17/693
    • A sample and hold circuit including a plurality of input signal sampling switches using native NMOS transistors in combination with switched bulk PMOS transistors. The input signal sampling switches input a differential input signal and output an intermediate differential signal. A plurality of capacitors are connected to the intermediate differential signal. A plurality of summing junction switches receive charge stored on the plurality of capacitors, and output a differential sampled and held charge to the summing junction. The plurality of input signal sampling switches include first, second, third, and fourth switches each having an input and an output. Inputs of the first and third switches are connected to a first voltage of the differential input voltage. Inputs of the second and fourth switches are connected to a second voltage of the differential input voltage. Outputs of the first and second switches are connected together and to an input of a first capacitor of the plurality of capacitors. Outputs of the third and fourth switches are connected together and to an input of a second capacitor of the plurality of capacitors.
    • 采样和保持电路包括使用天然NMOS晶体管与开关体PMOS晶体管组合的多个输入信号采样开关。 输入信号采样开关输入差分输入信号并输出​​中间差分信号。 多个电容器连接到中间差分信号。 多个求和结开关接收存储在多个电容器上的电荷,并且向加法结输出差分采样和保持的电荷。 多个输入信号采样开关包括具有输入和输出的第一,第二,第三和第四开关。 第一和第三开关的输入端连接到差分输入电压的第一电压。 第二和第四开关的输入连接到差分输入电压的第二电压。 第一和第二开关的输出端连接在一起并连接到多个电容器的第一电容器的输入端。 第三和第四开关的输出端连接在一起并连接到多个电容器的第二电容器的输入端。
    • 73. 发明申请
    • Amplifier compensation techniques for switched capacitor circuits
    • 开关电容电路的放大器补偿技术
    • US20050046460A1
    • 2005-03-03
    • US10835401
    • 2004-04-30
    • Sumant Ranganathan
    • Sumant Ranganathan
    • G06G7/18H03F1/34H03F3/00H03F3/45
    • H03F3/005H03F1/34H03F3/45475H03F2200/159H03F2203/45514
    • A system and method are used to maintain a variance in feedback factors of an amplifier between the first and second phases either below a threshold value or within a specified range. The system includes the amplifier and first through third capacitances. The amplifier is coupled between an input node and an output node that operates during first and second phases of operation. The first capacitance is coupled across the amplifier and between the input node and the output node during the first and second phases of operation. The second capacitance is coupled to the input node during the first phase of operation. The third capacitance is coupled to one of the input and output nodes during one or both of the first and second phases of operation.
    • 使用系统和方法来维持第一和第二相之间的放大器的反馈因子的差异,或者低于阈值或在指定范围内。 该系统包括放大器和第一至第三电容。 放大器耦合在输入节点和在第一和第二操作阶段期间操作的输出节点。 在操作的第一和第二阶段期间,第一电容跨越放大器并且在输入节点和输出节点之间耦合。 第二电容在第一阶段操作期间耦合到输入节点。 在操作的第一和第二阶段中的一个或两个期间,第三电容耦合到输入和输出节点中的一个。
    • 77. 发明授权
    • Line driver for an adaptive hybrid circuit
    • 自适应混合电路的线路驱动器
    • US08208462B2
    • 2012-06-26
    • US12497337
    • 2009-07-02
    • Tom KwanSumant Ranganathan
    • Tom KwanSumant Ranganathan
    • H04B3/23H04M9/08
    • H04L5/1423H04L25/0278
    • A second output transmission signal (“TX2”) added to a line driver is a scaled version of the main output transmission signal (“TX1”). TX2 is scaled from TX1 by a variable scale factor K. An adaptive hybrid circuit subtracts TX1 and TX2 from a line signal carrying both a line transmission signal and a line received signal (“RX”). A programmable impedance Ztune is coupled between the TX2 output of the line driver and the RX output of the adaptive hybrid circuit. A transmission echo in the output RX signal is measured. K and Ztune are then adaptively tuned to minimize the transmission echo. The hybrid in this case becomes a 4-port network, one port specifically added to adaptively cancel the transmission echo in the RX output of the adaptive hybrid circuit. Alternatively, the hybrid may be a 3-port hybrid including variable impedances to cancel the line transmission signal.
    • 添加到线路驱动器的第二输出发送信号(“TX2”)是主输出发送信号(“TX1”)的缩放版本。 TX2通过可变比例因子K从TX1缩放。自适应混合电路从携带线路传输信号和线路接收信号(“RX”)的线路信号中减去TX1和TX2。 可编程阻抗Ztune耦合在线路驱动器的TX2输出和自适应混合电路的RX输出之间。 测量输出RX信号中的传输回波。 然后自适应调整K和Ztune以最小化传输回波。 在这种情况下,混合器成为一个4端口网络,一个专门添加的端口自适应地消除了自适应混合电路的RX输出中的传输回波。 或者,混合动力可以是包括可变阻抗以消除线路传输信号的3端口混合器。
    • 79. 发明授权
    • On-chip amplifier/line driver compensation circuit
    • 片内放大器/线路驱动器补偿电路
    • US07282991B2
    • 2007-10-16
    • US10887869
    • 2004-07-12
    • Sumant Ranganathan
    • Sumant Ranganathan
    • H03F3/45
    • H03F1/08
    • An embodiment of the present invention includes an amplifier on an integrated circuit, with the amplifier having positive and negative inputs, and positive and negative outputs. A first feedback capacitor is on the integrated circuit between the positive input and the negative output. A second feedback capacitor is on the integrated circuit between the negative input and the positive output. A package encloses the integrated circuit. A third capacitor is between the positive and negative inputs. A feedback factor of the amplifier circuit approaches unity. In example embodiments, the first and second capacitors are between 3 and 10 pF. The third capacitor is between 3 and 10 pF.
    • 本发明的实施例包括集成电路上的放大器,放大器具有正和负输入以及正和负输出。 在正输入和负输出之间的集成电路上有第一个反馈电容。 负输入和正输出之间的集成电路上有第二个反馈电容。 封装封装集成电路。 第三个电容在正极和负极之间。 放大器电路的反馈系数接近一致。 在示例实施例中,第一和第二电容器在3和10pF之间。 第三电容器在3和10 pF之间。
    • 80. 发明授权
    • Sample and hold circuit based on an ultra linear switch
    • 基于超线性开关的采样和保持电路
    • US07119585B2
    • 2006-10-10
    • US10927416
    • 2004-08-27
    • Sumant Ranganathan
    • Sumant Ranganathan
    • G11C27/02
    • H03K17/063G11C27/02H03K17/6872H03K17/693
    • A sample and hold circuit including a plurality of input signal sampling switches using native NMOS transistors in combination with switched bulk PMOS transistors. The input signal sampling switches input a differential input signal and output an intermediate differential signal. A plurality of capacitors are connected to the intermediate differential signal. A plurality of summing junction switches receive charge stored on the plurality of capacitors, and output a differential sampled and held charge to the summing junction. The plurality of input signal sampling switches include first, second, third, and fourth switches each having an input and an output. Inputs of the first and third switches are connected to a first voltage of the differential input voltage. Inputs of the second and fourth switches are connected to a second voltage of the differential input voltage. Outputs of the first and second switches are connected together and to an input of a first capacitor of the plurality of capacitors. Outputs of the third and fourth switches are connected together and to an input of a second capacitor of the plurality of capacitors.
    • 采样和保持电路包括使用天然NMOS晶体管与开关体PMOS晶体管组合的多个输入信号采样开关。 输入信号采样开关输入差分输入信号并输出​​中间差分信号。 多个电容器连接到中间差分信号。 多个求和结开关接收存储在多个电容器上的电荷,并且向加法结输出差分采样和保持的电荷。 多个输入信号采样开关包括具有输入和输出的第一,第二,第三和第四开关。 第一和第三开关的输入端连接到差分输入电压的第一电压。 第二和第四开关的输入连接到差分输入电压的第二电压。 第一和第二开关的输出端连接在一起并连接到多个电容器的第一电容器的输入端。 第三和第四开关的输出端连接在一起并连接到多个电容器的第二电容器的输入端。