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71. 发明授权

US08169811B2 Non-volatile re-programmable memory device 有权
标题翻译：非易失性可重新编程存储器件
公开(公告)号：US08169811B2
公开(公告)日：2012-05-01
申请号：US12835588
申请日：2010-07-13
申请人： Yuan Li , Guoqiao Tao
发明人： Yuan Li , Guoqiao Tao
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C7/04 , G11C7/24 , G11C13/0007 , G11C13/0059 , H01L45/08 , H01L45/1226 , H01L45/14
摘要： A memory device including a non-volatile re-programmable memory cell is provided. In connection with various example embodiments, the memory cell is a single resistor located between a first and second node. The resistor stores different resistance states corresponding to different resistance values set by SiCr-facilitated migration. The SiCr-facilitated migration occurs in response to energy presented between the first and second nodes. The application of a signal to a first node of the memory cell resistor forces the migration of elements along the memory cell resistor to set the resistance value of the memory cell resistor. The application of a second signal of approximately equal strength to the second node reverses the change and resistance and returns the memory cell to the previous resistance level. In some implementations the resistor is made of SiCr.
摘要翻译：提供了包括非易失性可再编程存储单元的存储器件。结合各种示例实施例，存储器单元是位于第一和第二节点之间的单个电阻器。电阻器存储对应于由SiCr促进迁移设置的不同电阻值的不同电阻状态。 SiCr促进的迁移响应于第一和第二节点之间的能量而发生。将信号施加到存储单元电阻器的第一节点迫使元件沿着存储单元电阻器的迁移以设置存储单元电阻器的电阻值。对第二节点施加大致相等强度的第二信号反转该变化和电阻，并将存储器单元返回到先前的电阻电平。在一些实施方案中，电阻器由SiCr制成。

72. 发明申请

US20100315960A1 METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR PROVIDING ADAPTIVE JITTER BUFFER MANAGEMENT BASED ON PACKET STATISTICS FOR MEDIA GATEWAY 有权
标题翻译：方法，系统和计算机可读介质，用于提供基于媒体网关的分组统计的自适应抖动缓冲区管理
公开(公告)号：US20100315960A1
公开(公告)日：2010-12-16
申请号：US12482217
申请日：2009-06-10
申请人： Yuan Li
发明人： Yuan Li
IPC分类号： H04L12/26
CPC分类号： H04L43/087 , H04L1/205 , H04L41/0803 , H04L43/00 , H04L47/283
摘要： Methods, systems, and computer readable media for providing adaptive jitter buffer management based on packet statistics for media gateway are disclosed. According to one aspect, the subject matter described herein includes a system for providing adaptive jitter buffer management based on packet statistics for a media gateway. The system includes a media gateway for communicating data between entities in one or more telecommunication networks. The media gateway includes first and second network interfaces for interfacing with the one or more telecommunication networks, a packet monitor for monitoring and maintaining packet statistics for channels established between the first and second network interfaces, each channel including a jitter buffer for buffering packets received on the first or second network interface, and a jitter buffer adjustment module for dynamically adjusting jitter buffer size on a per-channel basis based on the packet statistics maintained for each channel.
摘要翻译：公开了用于基于媒体网关的分组统计提供自适应抖动缓冲器管理的方法，系统和计算机可读介质。根据一个方面，本文描述的主题包括用于基于媒体网关的分组统计提供自适应抖动缓冲器管理的系统。该系统包括用于在一个或多个电信网络中的实体之间传送数据的媒体网关。媒体网关包括用于与一个或多个电信网络对接的第一和第二网络接口，用于监视和维护在第一和第二网络接口之间建立的信道的分组统计的分组监视器，每个信道包括用于缓冲接收到的分组的抖动缓冲器第一或第二网络接口以及抖动缓冲器调整模块，用于基于为每个信道维护的分组统计信息在每个信道的基础上动态地调整抖动缓冲器大小。

73. 发明授权

US07834142B2 Shortened glucagon-like peptide 1(sGLP-1) preparation method and application 有权
标题翻译：缩短胰高血糖素样肽1（sGLP-1）的制备方法和应用
公开(公告)号：US07834142B2
公开(公告)日：2010-11-16
申请号：US11665277
申请日：2006-03-30
申请人： Yuan Li
发明人： Yuan Li
IPC分类号： C07K14/605
CPC分类号： C07K14/605 , A61K38/00 , C07K14/61
摘要： This invention relates to similar compound of glucagon-like peptide 1 (glucagon-like peptide-1, GLP-1) secreted by insulinotropic hormone, i.e. shortened glucagon-like peptide 1 (sGLP-1) consisting of 26 aminoacids. Its sequence is as follows: His-X1-Glu-Gly-Thr-Phe-Thr-Ser-Asp-Val-Ser-Ser-Tyr-Leu-Glu-Gly-Gln-Ala-Ala-Lys-Glu-Phe-Ile-Ala-Trp-Leu (SEQ ID NO: 2). In comparison with the present GLP-1 and its similar compound, the shortened glucagon-like peptide 1 (sGLP-1) in this invention has the following prominent advantages: 1. After reconstruction, the shortened peptide chain has stronger simulation to islet cell captors and stronger insulin secretion stimulation action; 2. the reconstructed simulation sequence can resist dipeptidyl peptidase decomposition by change of the second aminoacid sequence from Ala to Gly or Ser to prolong its half time and enhance drug action; 3. To shorten the peptide chain leads to reduced synthesis cost.
摘要翻译：本发明涉及由胰岛素激素分泌的胰高血糖素样肽1（胰高血糖素样肽-1，GLP-1）的类似化合物，即由26个氨基酸组成的缩短的胰高血糖素样肽1（sGLP-1）。其序列如下：His-X1-Glu-Gly-Thr-Phe-Thr-Ser-Asp-Val-Ser-Ser-Tyr-Leu-Glu-Gly-Gln-Ala-Ala-Lys-Glu-Phe- Ile-Ala-Trp-Leu（SEQ ID NO：2）。与本发明的GLP-1及其类似化合物相比，本发明中胰高血糖素样肽1（sGLP-1）的缩短具有以下突出优点：1.重建后，缩短的肽链具有更强的模拟胰岛细胞捕获和更强的胰岛素分泌刺激作用; 2.重建的模拟序列可以通过将第二个氨基酸序列从Ala改变为Gly或Ser来延长其半衰期并增强药物作用，从而抵抗二肽基肽酶的分解; 缩短肽链导致合成成本降低。

74. 发明申请

US20100195870A1 TRACKING METHOD AND DEVICE ADOPTING A SERIES OF OBSERVATION MODELS WITH DIFFERENT LIFE SPANS 有权
标题翻译：跟踪方法和设备采用不同生活模式的观察模型系列
公开(公告)号：US20100195870A1
公开(公告)日：2010-08-05
申请号：US12664588
申请日：2008-06-13
申请人： Haizhou Ai , Yuan Li , Shihong Lao , Takayoshi Yamashita
发明人： Haizhou Ai , Yuan Li , Shihong Lao , Takayoshi Yamashita
IPC分类号： G06K9/62
CPC分类号： G06T7/277 , G06T2207/10016 , G06T2207/30201
摘要： The present invention relates to a tracking method and a tracking device adopting multiple observation models with different life spans. The tracking method is suitable for tracking an object in a low frame rate video or with abrupt motion, and uses three observation models with different life spans to track and detect a specific subject in frame images of a video sequence. An observation model I performs online learning with one frame image prior to the current image, an observation model II performs online learning with five frames prior to the current image, and an observation model III is offline trained. The three observation models are combined by a cascade particle filter so that the specific subject in the low frame rate video or the object with abrupt motion can be tracked quickly and accurately.
摘要翻译：本发明涉及采用具有不同寿命的多个观察模型的跟踪方法和跟踪装置。跟踪方法适用于跟踪低帧率视频或突然运动的对象，并且使用具有不同寿命的三个观察模型来跟踪和检测视频序列的帧图像中的特定主体。观察模型I在当前图像之前用一帧图像执行在线学习，观察模型II在当前图像之前用五帧执行在线学习，并且观察模型III被离线训练。三个观察模型通过级联粒子滤波器组合，使得低帧率视频中的特定对象或具有突然运动的对象能够被快速准确地跟踪。

75. 发明授权

US07741160B1 Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate 有权
标题翻译：针对低K Si和薄芯基板设计的低应力薄晶片倒装芯片封装的结构和组装程序
公开(公告)号：US07741160B1
公开(公告)日：2010-06-22
申请号：US12535624
申请日：2009-08-04
申请人： Wen-chou Vincent Wang , Yuan Li , Bruce Euzent , Vadali Mahadev
发明人： Wen-chou Vincent Wang , Yuan Li , Bruce Euzent , Vadali Mahadev
IPC分类号： H01L21/44
CPC分类号： H01L23/3128 , H01L21/50 , H01L21/563 , H01L23/16 , H01L24/31 , H01L24/81 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81801 , H01L2924/01019 , H01L2924/0102 , H01L2924/01322 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/16195 , H01L2924/00 , H01L2924/3512
摘要： Provided are semiconductor die flip chip packages and semiconductor die flip chip package components where certain properties of the packages/components are controlled to facilitate management of the package stresses. Also provided are fabrication methods for such packages and package components. For instance, the thickness of a die can be controlled such that the stress generated/experienced by the die is minimized. As such, the package stress is managed to suitable levels for incorporation of a low-K Si die and/or a thin package substrate. Further, a thin die can be attached to a heat spreader to increase the rigidity for easier handling during fabrication of the semiconductor die flip chip package.
摘要翻译：提供了半导体管芯倒装芯片封装和半导体管芯倒装芯片封装元件，其中封装/部件的某些特性被控制以便于封装应力的管理。还提供了用于这种包装和包装部件的制造方法。例如，可以控制模具的厚度，使得由模具产生/经历的应力最小化。因此，封装应力被控制到适合于并入低K Si管芯和/或薄封装衬底的水平。此外，在半导体管芯倒装芯片封装的制造期间，可以将薄模具附接到散热器以增加刚性以便于更容易的处理。

76. 发明申请

US20090287619A1 Differentiated, Integrated and Individualized Education 有权
标题翻译：差异化，综合性和个性化教育
公开(公告)号：US20090287619A1
公开(公告)日：2009-11-19
申请号：US12121249
申请日：2008-05-15
申请人： Changnian Liang , Pingyi Yan , Xiaofeng Zhang , Yuan Li
发明人： Changnian Liang , Pingyi Yan , Xiaofeng Zhang , Yuan Li
IPC分类号： G06F17/00
CPC分类号： G06Q50/20
摘要： A computer-based learning system uses knowledge points organized with a predefined multilevel arrangement. Each knowledge point has an information set which may include a knowledge content, an evaluation content and a solution content. For a given knowledge point, the learning system provides the knowledge content and evaluation content, analyzes the user's answers to the evaluation content and determines the next knowledge point to be studied by the user based on the user's answers and the predefined multilevel arrangement of the knowledge points. The learning system thus provides a different learning course for different users to achieve individualized learning. User's learning history may be recorded to facilitate reviews by the user and improve the selection of the next knowledge point. Users may provide feedbacks on knowledge contents and evaluation contents, and may even suggest their own knowledge contents and evaluation contents to improve the learning system and user participation.
摘要翻译：基于计算机的学习系统使用以预定义多级布置组织的知识点。每个知识点具有可以包括知识内容，评估内容和解决方案内容的信息集。对于给定的知识点，学习系统提供知识内容和评估内容，分析用户对评估内容的答案，并根据用户的答案和知识的预定义多层次排列确定用户要研究的下一个知识点积分因此，学习系统为不同用户提供了不同的学习课程，以实现个性化学习。可以记录用户的学习历史以促进用户的评论并改进下一个知识点的选择。用户可以提供知识内容和评估内容的反馈意见，甚至可以提出自己的知识内容和评估内容，以改善学习系统和用户参与。

77. 发明申请

US20090180495A1 Method for Transmitting Data, Method for Receiving Data, Transmitter, Receiver, and Computer Program Products 有权
标题翻译：发送数据的方法，接收数据的方法，发送器，接收器和计算机程序产品
公开(公告)号：US20090180495A1
公开(公告)日：2009-07-16
申请号：US11815381
申请日：2006-02-02
申请人： Yuan Li , Sumei Sun , Yan Wu
发明人： Yuan Li , Sumei Sun , Yan Wu
IPC分类号： H04J13/00 , H04L27/36 , H04L27/00
CPC分类号： H04L1/0041 , H03M13/11 , H03M13/1148 , H03M13/255 , H03M13/356 , H04L1/0058 , H04L1/0071 , H04L5/0023 , H04L27/34 , H04L2001/0098
摘要： A method for transmitting data comprising a plurality of bits is described wherein the data is mapped to a plurality of modulation symbols, each modulation symbol comprising at least one more significant bit and at least one less significant bit, at least one parity bit is generated for the plurality of bits and the plurality of bits are mapped to more significant bits of the plurality of modulation symbols and the at least one parity bit is mapped to at least one less significant bit of the plurality of modulation symbols.
摘要翻译：描述了一种用于发送包括多个位的数据的方法，其中将数据映射到多个调制符号，每个调制符号包括至少一个更高有效位和至少一个较低有效位，至少一个奇偶校验位被产生用于多个位和多个位被映射到多个调制符号中的更高有效位，并且至少一个奇偶校验位被映射到多个调制符号中的至少一个较低有效位。

78. 发明授权

US07459782B1 Stiffener for flip chip BGA package 有权
标题翻译：加强器用于倒装芯片BGA封装
公开(公告)号：US07459782B1
公开(公告)日：2008-12-02
申请号：US11244953
申请日：2005-10-05
申请人： Yuan Li
发明人： Yuan Li
IPC分类号： H01L23/14
CPC分类号： H01L23/373 , H01L23/3128 , H01L23/36 , H01L23/49833 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01322 , H01L2924/10253 , H01L2924/15311 , H01L2924/16195 , H01L2924/00 , H01L2224/0401
摘要： Provided are semiconductor die flip chip packages with warpage control and fabrication methods for such packages. A package includes a heat spreader that is attached to a die and a stiffener, which are in turn attached to a package substrate. In general, the stiffener is made of a material that has a relatively low CTE value. For example, the stiffener material may have a CTE value less than 12 ppm/° C. The material may also have a relatively low mass density value of less than 8.9 g/cm3. Such a material may include natural graphite or some composite form of it. The result is a package with less bowing and so improved co-planarity (e.g., in compliance with industry specifications) with the surface to which it is ultimately bound; thereby, improving the reliability of the package. Moreover, a package that is relatively lighter and more robust than conventional semiconductor die flip chip packages can be realized.
摘要翻译：提供了具有翘曲控制的半导体管芯倒装芯片封装以及用于这种封装的制造方法。一个包装件包括一个附着在模具和一个加强件上的散热器，该加强件又连接在一个封装基板上。通常，加强件由具有较低CTE值的材料制成。例如，加强材料可以具有小于12ppm /℃的CTE值。材料还可以具有小于8.9g / cm 3的相对低的质量密度值。这种材料可以包括天然石墨或其一些复合形式。结果是具有较少弓形和如此改进的共面性（例如，符合行业规范）与其最终结合的表面的包装; 从而提高包装的可靠性。此外，可以实现比常规半导体管芯倒装芯片封装相对更轻且更坚固的封装。

79. 发明授权

US07427813B1 Structure, material, and design for assembling a low-K Si die to achieve an industrial grade reliability wire bonding package 有权
标题翻译：用于组装低K Si模具的结构，材料和设计，以实现工业级可靠性引线接合封装
公开(公告)号：US07427813B1
公开(公告)日：2008-09-23
申请号：US10719218
申请日：2003-11-20
申请人： Wen-chou Vincent Wang , Yuan Li
发明人： Wen-chou Vincent Wang , Yuan Li
IPC分类号： H01L29/40 , H01L23/28 , H01L23/29
CPC分类号： H01L23/3185 , H01L23/3107 , H01L23/3128 , H01L23/3142 , H01L23/3171 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/10253 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： Provided are semiconductor low-K Si die wire bonding packages with package stress control and fabrication methods for such packages. The packages include molding interface material applied onto the low-K Si die. In general, the molding interface material is selectively applied onto the low-K Si die surface in order to minimize to safe levels the package stress experienced by the low-K Si die. Selective application includes defining various combinatorial patterns of coated and non-coated regions. In addition, selective application may also include a general application of molding interface material to create a stress buffer zone. The results are packages with less stress experienced by the low-K Si die and so improved reliability (in compliance with industry specifications).
摘要翻译：提供具有封装应力控制的半导体低K Si芯线焊接封装和用于这种封装的制造方法。包装包括施加到低K Si模具上的成型界面材料。通常，将成型界面材料选择性地施加到低K Si晶粒表面上，以便最小化由低K Si晶粒经受的封装应力的安全水平。选择性应用包括定义涂层和非涂层区域的各种组合图案。此外，选择性应用还可以包括模制界面材料的一般应用以产生应力缓冲区。结果是低K Si模具经受较少应力的封装，从而提高了可靠性（符合行业规范）。

80. 发明申请

US20080129722A1 Liquid crystal display having control circuit for delay gradation voltages and driving method thereof 有权
标题翻译：具有用于延迟灰度电压的控制电路的液晶显示器及其驱动方法
公开(公告)号：US20080129722A1
公开(公告)日：2008-06-05
申请号：US11999102
申请日：2007-12-03
申请人： Xiao-Jing Qi , Yuan Li
发明人： Xiao-Jing Qi , Yuan Li
IPC分类号： G06F3/038
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2320/0233
摘要： An exemplary liquid crystal display (LCD) (200) includes an LCD panel having a plurality of display regions (240) arranged sequentially; a plurality of gate driving circuit (250) respectively connected to the display regions for providing scan signal to scanning the display region; at least a data driving circuit (230) for generating gradation voltages and providing the gradation voltages to the corresponding scanned display region; and a delay control circuit connected between the data driving circuit and the display regions for delaying the gradation voltages provided to each display region. The sum of the first delay value generated by the delay control circuit when the gradation voltages are applied to one of the display regions and the second delay value of the same gradation voltages being generated when the gradation voltages are transmitted from the gate driving circuit to the same one of the display regions is approximately constant for all of the display regions.
摘要翻译：示例性液晶显示器（LCD）（200）包括具有顺序布置的多个显示区域（240）的LCD面板; 分别连接到显示区域的多个栅极驱动电路（250），用于提供扫描信号以扫描显示区域; 至少一个用于产生灰度电压并将灰度电压提供给相应扫描的显示区域的数据驱动电路（230）以及延迟控制电路，连接在数据驱动电路和显示区域之间，用于延迟提供给每个显示区域的灰度电压。当灰度电压被施加到一个显示区域时由延迟控制电路产生的第一延迟值和当灰度电压从栅极驱动电路传输到相同灰度电压时产生的第二延迟值的总和对于所有显示区域，相同的一个显示区域近似恒定。

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