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71. 发明申请

US20050202323A1 Phase shift mask and method of manufacturing phase shift mask 审中-公开
标题翻译：相移掩模和相移掩模的制造方法
公开(公告)号：US20050202323A1
公开(公告)日：2005-09-15
申请号：US11022700
申请日：2004-12-28
申请人： Kunio Watanabe
发明人： Kunio Watanabe
IPC分类号： G03F1/30 , G03F1/58 , G03F1/68 , G03F7/20 , G03F9/00 , H01L21/027
CPC分类号： G03F1/30
摘要： A phase shift mask comprises a transparent substrate and a light shielding film. The transparent substrate has two regions that transmit exposure light. The exposure light transmitted through one region having a phase that is inverted in a recessed portion formed in the other region. The light shielding film shields the exposure light. The light shielding film is formed on the transparent substrate with a plurality of film thicknesses and has an edge that does not hang over the recessed portion.
摘要翻译：相移掩模包括透明基板和遮光膜。透明基板具有透射曝光光的两个区域。曝光光透过一个区域，该区域具有形成在另一区域中的凹部中被倒置的相位。遮光膜屏蔽曝光灯。遮光膜形成在多个膜厚度的透明基板上，并且具有不悬在凹部上的边缘。

72. 发明授权

US06664603B2 Semiconductor device, memory system and electronic apparatus 失效
公开(公告)号：US06664603B2
公开(公告)日：2003-12-16
申请号：US10153430
申请日：2002-05-21
申请人： Junichi Karasawa , Kunio Watanabe
发明人： Junichi Karasawa , Kunio Watanabe
IPC分类号： H01L2976
CPC分类号： H01L27/1104 , Y10S257/903
摘要： A semiconductor device having a memory cell including first and second load transistors, first and second driver transistors, and first and second transfer transistors. The semiconductor device includes a first gate-gate electrode layer and a first drain-gate wiring layer. A distance L1 between the edges of the first drain-gate wiring layer and an active region of the first driver transistor is greater than or equal to a distance L2 between the first drain-gate wiring layer and an active region of the first load transistor. This structure provides semiconductor devices in which memory cells having desired characteristics can be readily fabricated. The invention also provides memory systems and electronic apparatuses which include the above semiconductor devices.

73. 发明授权

US06656271B2 Method of manufacturing semiconductor wafer method of using and utilizing the same 失效
标题翻译：使用和利用半导体晶片方法的方法
公开(公告)号：US06656271B2
公开(公告)日：2003-12-02
申请号：US09453539
申请日：1999-12-03
申请人： Takao Yonehara , Kunio Watanabe , Tetsuya Shimada , Kazuaki Ohmi , Kiyofumi Sakaguchi
发明人： Takao Yonehara , Kunio Watanabe , Tetsuya Shimada , Kazuaki Ohmi , Kiyofumi Sakaguchi
IPC分类号： C30B2518
CPC分类号： H01L21/76251 , H01L21/76259 , Y10S117/913
摘要： A process for manufacturing a semiconductor wafer which has superior suitability for mass production and reproducibility. The process comprises the steps of preparing a first member which has a monocrystalline semiconductor layer on a semiconductor substrate with a separation layer arranged therebetween with a semiconductor wafer as the raw material, transferring the monocrystalline semiconductor layer onto a second member which comprises a semiconductor wafer after separating the monocrystalline semiconductor layer through the separation layer, and smoothing the surface of the semiconductor substrate after the transferring step so as to be used as a semiconductor wafer for purposes other than forming the first and second members.
摘要翻译：一种半导体晶片的制造方法，其具有优异的批量生产和再现性的适用性。该方法包括以下步骤：在半导体衬底上制备具有单晶半导体层的第一构件，其间分隔层以半导体晶片为原料，将单晶半导体层转移到第二构件上，该第二构件包括半导体晶片通过分离层分离单晶半导体层，并且在转印步骤之后使半导体衬底的表面平滑，以便用作除了形成第一和第二构件之外的目的的半导体晶片。

74. 发明授权

US06468923B1 Method of producing semiconductor member 失效
标题翻译：半导体部件的制造方法
公开(公告)号：US06468923B1
公开(公告)日：2002-10-22
申请号：US09534340
申请日：2000-03-24
申请人： Takao Yonehara , Kunio Watanabe , Tetsuya Shimada , Kazuaki Ohmi , Kiyofumi Sakaguchi
发明人： Takao Yonehara , Kunio Watanabe , Tetsuya Shimada , Kazuaki Ohmi , Kiyofumi Sakaguchi
IPC分类号： H01L2131
CPC分类号： H01L21/0203 , C25D11/32 , H01L21/0237 , H01L21/02381 , H01L21/0245 , H01L21/02513 , H01L21/02521 , H01L21/02532 , H01L21/0262 , H01L21/76254 , H01L21/76259
摘要： A method of producing a semiconductor member comprises a first step of preparing a first member having a non-porous layer on a semiconductor substrate, and a second step of transferring the non-porous layer from the first member onto a second member, wherein use of the semiconductor substrate from which the non-porous layer is separated in the second step as a constituent material of the first member in the first step is conducted (n−1) times (“n” is a natural number not less than 2), the first and second steps are repeated n times, the semiconductor substrate is separated in n-th use in the second step and the separated semiconductor substrate is used for an use other than that of the first and second steps.
摘要翻译：制造半导体构件的方法包括：在半导体衬底上制备具有无孔层的第一构件的第一步骤和将第一构件的无孔层转移到第二构件上的第二步骤，其中使用进行第一步骤中作为第一部件的构成材料的第二步骤中的无孔层从其分离的半导体衬底（n-1）次（“n”是不小于2的自然数），第一步骤和第二步骤重复n次，在第二步骤中第n次使用半导体衬底被分离，并且分离的半导体衬底用于除了第一和第二步骤之外的用途。

75. 发明授权

US06311389B1 Gradient magnetic coil apparatus and method of manufacturing the same 有权
标题翻译：梯度电磁线圈装置及其制造方法
公开(公告)号：US06311389B1
公开(公告)日：2001-11-06
申请号：US09343400
申请日：1999-06-30
申请人： Yasuhiro Uosaki , Kunio Watanabe , Masatoshi Yamashita , Yoshitomo Sakakura
发明人： Yasuhiro Uosaki , Kunio Watanabe , Masatoshi Yamashita , Yoshitomo Sakakura
IPC分类号： H01F706
CPC分类号： G01R33/3858 , G01R33/3856 , H01F41/041 , Y10T29/49071 , Y10T29/49073
摘要： A curved metal plate is adhered to an outer surface of a cylindrical jig of the same shape, the metal plate is cut along the spiral coil winding pattern, the unnecessary metal portion other than the coil winding is peeled off from the jig to leave only the coil winding on the jig, an adhesive is applied on the coil winding, and an insulating sheet is covered over the jig (the coil winding thereon). After the coil winding is adhered to the insulating sheet, the insulating sheet (together with the coil winding) is peeled off from the jig. As a result, a saddle coil adhering the spiral coil winding to the inner side of the curved cylindrical insulating sheet is manufactured. According to such manufacturing method, without requiring huge equipment such as drying furnace, the saddle coil having a desired winding pattern with high precision can be manufactured in a short time and at low cost.
摘要翻译：将弯曲的金属板粘附到相同形状的圆柱形夹具的外表面上，沿着螺旋线圈绕线图案切割金属板，除了线圈绕组之外的不必要的金属部分从夹具上剥离，仅留下线圈缠绕在夹具上，将粘合剂施加在线圈绕组上，并且绝缘片被覆盖在夹具上（线圈绕在其上）。在线圈绕组粘附到绝缘片上之后，将绝缘片（与线圈绕组一起）从夹具上剥离。结果，制造将螺旋线圈绕组附接到弯曲圆柱形绝缘片的内侧的鞍形线圈。根据这种制造方法，不需要诸如干燥炉等大型设备，能够在短时间内以低成本制造具有高精度的期望的卷绕图案的鞍形线圈。

76. 发明授权

US06243286B1 Semiconductor memory device and method of fabricating the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06243286B1
公开(公告)日：2001-06-05
申请号：US09361095
申请日：1999-07-26
申请人： Takashi Kumagai , Junichi Karasawa , Kazuo Tanaka , Kunio Watanabe
发明人： Takashi Kumagai , Junichi Karasawa , Kazuo Tanaka , Kunio Watanabe
IPC分类号： G11C1100
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903
摘要： An SRAM comprises first, second and third conductive layers. The first conductive layer is a gate electrode for a first load transistor and a first driver transistor. The second conductive layer branches from the first conductive layer on a field oxide region and is electrically connected to a second driver transistor active region. The third conductive layer is a gate electrode for a second load transistor and a second driver transistor. The third conductive layer is electrically connected to a first load transistor active region. The width of part of the second conductive layer on the field oxide region is less than the width of the first conductive layer.
摘要翻译： SRAM包括第一，第二和第三导电层。第一导电层是用于第一负载晶体管和第一驱动晶体管的栅电极。第二导电层在场氧化物区域上从第一导电层分支并且电连接到第二驱动晶体管有源区。第三导电层是用于第二负载晶体管的栅电极和第二驱动晶体管。第三导电层电连接到第一负载晶体管有源区。场氧化物区域上的第二导电层的一部分的宽度小于第一导电层的宽度。

77. 发明授权

US6162567A Process for producing halftone mask 有权
标题翻译：生产半色调面膜的方法
公开(公告)号：US6162567A
公开(公告)日：2000-12-19
申请号：US372089
申请日：1999-08-11
申请人： Kunio Watanabe
发明人： Kunio Watanabe
IPC分类号： G03F1/68 , G03F1/76 , G03F1/78 , G03F1/80 , H01L21/027 , G03F9/00
CPC分类号： G03F1/50 , Y10S430/143
摘要： A process for producing a halftone mask comprises the steps of: (a) forming an electron beam resist film on a mask blank which includes a translucent film and a light-block film sequentially formed on a transparent substrate; (b) irradiating an electron beam to the electron beam resist film in such a dose that the electron beam resist film remains in a predetermined thickness by development in a first write area and is completely removed by development in a second write area; (c) developing the electron beam resist film thereby to form an electron beam resist film retaining the predetermined thickness in the first write area and having an opening in the second write area; (d) patterning the light-block film using the resulting electron beam resist film as a mask; (e) ashing the electron beam resist film to remove the electron beam resist film from the first write area completely; (f) patterning the translucent film using the patterned light-block film as a mask; and (g) patterning the light-block film using the resulting electron beam resist film as a mask.
摘要翻译：一种制造半色调掩模的方法包括以下步骤：（a）在掩模板上形成电子束抗蚀剂膜，该掩模板包括依次形成在透明基板上的半透明膜和光阻挡膜; （b）以电子束抗蚀剂膜的电子束照射电子束，其电子束抗蚀剂膜通过在第一写入区域中的显影而保持在预定厚度，并且在第二写入区域中通过显影完全去除; （c）显影电子束抗蚀剂膜，从而形成在第一写入区域中保持预定厚度并在第二写入区域中具有开口的电子束抗蚀剂膜; （d）使用所得的电子束抗蚀剂膜作为掩模对所述光阻挡膜进行构图; （e）使电子束抗蚀剂膜从第一写入区域完全去除电子束抗蚀剂膜; （f）使用所述图案化阻挡膜作为掩模来图案化所述半透明膜; 和（g）使用所得到的电子束抗蚀剂膜作为掩模来图案化光阻挡膜。

78. 发明授权

US6081016A CMOS device with improved wiring density 有权
标题翻译：具有改善布线密度的CMOS器件
公开(公告)号：US6081016A
公开(公告)日：2000-06-27
申请号：US282035
申请日：1999-03-30
申请人： Kazuo Tanaka , Takashi Kumagai , Junichi Karasawa , Kunio Watanabe
发明人： Kazuo Tanaka , Takashi Kumagai , Junichi Karasawa , Kunio Watanabe
IPC分类号： H01L21/28 , H01L21/285 , H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L27/092 , H01L27/11 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11 , H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L27/1104
摘要： A method of manufacturing a semiconductor device comprising the following steps: forming first, second, and third wiring layers on a semiconductor substrate; forming first, second, and third cover dielectric layers for covering these wiring layers; forming a first impurity diffusion layer of a P type and a second impurity diffusion layer of an N type in an active region, and forming a third impurity diffusion layer of a P type and a fourth impurity diffusion layer cf an N type in an active region; self-alignably forming a first local wiring layer for connecting the first impurity diffusion layer with the second wiring layer, and self-alignably forming a second local wiring layer for connecting the fourth impurity diffusion layer with the third wiring layer; in an interlayer dielectric layer, self-alignably forming a first contact hole by using the first and third cover dielectric layers as masking layers, and self-alignably forming a second contact hole by using the second cover dielectric layer as a masking layer; and forming fourth and fifth wiring layers in these contact holes, respectively.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在半导体衬底上形成第一，第二和第三布线层; 形成用于覆盖这些布线层的第一，第二和第三覆盖电介质层; 在有源区中形成P型和N型的第二杂质扩散层的第一杂质扩散层，在有源区中形成N型的P型和第四杂质扩散层的第三杂质扩散层 ; 自对准地形成用于将第一杂质扩散层与第二布线层连接的第一局部布线层，并自对准地形成用于将第四杂质扩散层与第三布线层连接的第二局部布线层; 在层间电介质层中，通过使用第一和第三覆盖电介质层作为掩蔽层自对准地形成第一接触孔，并且通过使用第二覆盖电介质层作为掩蔽层自对准地形成第二接触孔; 并且在这些接触孔中分别形成第四和第五布线层。

79. 发明授权

US6034432A Thin film transistors and connecting structure for semiconductors and a method of manufacturing the same 失效
标题翻译：薄膜晶体管和半导体的连接结构及其制造方法
公开(公告)号：US6034432A
公开(公告)日：2000-03-07
申请号：US750760
申请日：1997-03-10
申请人： Junichi Karasawa , Kunio Watanabe
发明人： Junichi Karasawa , Kunio Watanabe
IPC分类号： H01L21/8244 , H01L27/11 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/11 , H01L27/1108 , Y10S257/903
摘要： A metallic layer (10), a thin-film first polycrystalline silicon layer (14), a first contact hole for connecting the metallic layer and first polycrystalline silicon layer, a second polycrystalline silicon layer (18) which becomes an etching stopper layer for the prevention of penetration in the first contact hole area, and a second contact hole which connects the second polycrystalline silicon layer and the first polycrystalline silicon layer are included. P-type impurities are introduced into the first polycrystalline silicon layer, and the second polycrystalline silicon layer is non-doped in the first contact hole area. By a heating step, the P-type impurities in the first polycrystalline silicon layer are diffused to the second polycrystalline silicon layer. The second polycrystalline silicon layer is N-type in a memory cell area. An insulating layer may be formed into a concave shape in the first contact hole area to lower the height of the first polycrystalline silicon layer in the first contact hole area.
摘要翻译： PCT No.PCT / JP96 / 01047 Sec。 371日期1997年3月10日 102（e）1997年3月10日PCT PCT 1996年4月17日PCT公布。第WO96 / 33512号公报日期：1996年10月24日金属层（10），薄膜第一多晶硅层（14），用于连接金属层和第一多晶硅层的第一接触孔，第二多晶硅层（18）用于防止在第一接触孔区域中穿透的蚀刻阻挡层，以及连接第二多晶硅层和第一多晶硅层的第二接触孔。 P型杂质被引入到第一多晶硅层中，并且第二多晶硅层在第一接触孔区域中未被掺杂。通过加热步骤，第一多晶硅层中的P型杂质扩散到第二多晶硅层。第二多晶硅层是存储单元区域中的N型。绝缘层可以在第一接触孔区域中形成为凹形，以降低第一接触孔区域中的第一多晶硅层的高度。

80. 发明授权

US5636254A Signal processing delay circuit 失效
标题翻译：信号处理延迟电路
公开(公告)号：US5636254A
公开(公告)日：1997-06-03
申请号：US430534
申请日：1995-04-25
申请人： Kenichi Hase , Ryutaro Horita , Kunio Watanabe , Yoshiteru Ishida , Takashi Nara , Hiroshi Kimura
发明人： Kenichi Hase , Ryutaro Horita , Kunio Watanabe , Yoshiteru Ishida , Takashi Nara , Hiroshi Kimura
IPC分类号： G11B5/09 , G11B20/10 , G11B20/14 , H03H11/26 , H03H11/54 , H03K5/13 , H03K5/135 , H03L7/081 , H03L7/089 , H03L7/099 , H04L7/00 , H04L7/02
CPC分类号： H03L7/0805 , G11B20/10 , G11B20/1403 , H03K5/13 , H03L7/0812 , H03L7/0896 , H03L7/0995 , H04L7/02 , H04L7/0008 , H04L7/0041
摘要： A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit.
摘要翻译：制造信号处理延迟电路作为半导体积分电路，以应对数据传送速度的增加和记录介质上的数据记录和再现密度。在延迟电路中，延迟PLL的参考延迟电路的延迟量被控制为独立于半导体电路的质量偏差，功率变化和温度变化的固定值。采用监视参考延迟电路的延迟量的控制信号来控制提供给窗口调整电路的窗口调整延迟电路的输入信号的延迟量和产生同步信号的T / 2产生延迟电路。这些延迟电路中的每一个包括具有相同配置的模拟可变延迟电路。窗口调整延迟电路由通过D / A转换器对控制信号进行加权而获得的信号进行监视。数据采集电路和数据写入电路各自包括模拟可变延迟电路。

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