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71. 发明授权

US08525289B2 Adjusting threshold voltage for sophisticated transistors by diffusing a gate dielectric cap layer material prior to gate dielectric stabilization 有权
标题翻译：通过在栅极电介质稳定之前扩散栅介质盖层材料来调整复杂晶体管的阈值电压
公开(公告)号：US08525289B2
公开(公告)日：2013-09-03
申请号：US13444955
申请日：2012-04-12
申请人： Richard Carter , Martin Trentzsch , Sven Beyer , Rohit Pal
发明人： Richard Carter , Martin Trentzsch , Sven Beyer , Rohit Pal
IPC分类号： H01L23/58
CPC分类号： H01L21/823462 , H01L21/28176 , H01L21/28194 , H01L29/513 , H01L29/517
摘要： Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.
摘要翻译：复杂的栅极电极结构可以通过在进行用于稳定敏感栅极介电材料的处理之前提供包括可能扩散到栅极电介质材料中的所需物质的覆盖层来形成。以这种方式，与常规策略相比，可以基于用于阈值调节物质的降低的温度和剂量来形成复杂的高k金属栅电极结构。此外，可以为两种类型的晶体管沉积单个含金属的电极材料。

72. 发明授权

US08524591B2 Maintaining integrity of a high-K gate stack by passivation using an oxygen plasma 有权
标题翻译：使用氧等离子体通过钝化保持高K栅极堆叠的完整性
公开(公告)号：US08524591B2
公开(公告)日：2013-09-03
申请号：US12848644
申请日：2010-08-02
申请人： Sven Beyer , Rick Carter , Andreas Hellmich , Berthold Reimer
发明人： Sven Beyer , Rick Carter , Andreas Hellmich , Berthold Reimer
IPC分类号： H01L29/78 , H01L21/336 , H01L21/28
CPC分类号： H01L21/28247 , H01L21/0206 , H01L21/02244 , H01L29/4966 , H01L29/517 , H01L29/6656 , H01L29/7848
摘要： In semiconductor devices, integrity of a titanium nitride material may be increased by exposing the material to an oxygen plasma after forming a thin silicon nitride-based material. The oxygen plasma may result in an additional passivation of any minute surface portions which may not be appropriately covered by the silicon nitride-based material. Consequently, efficient cleaning recipes, such as cleaning processes based on SPM, may be performed after the additional passivation without undue material loss of the titanium nitride material. In this manner, sophisticated high-k metal gate stacks may be formed with a very thin protective liner material on the basis of efficient cleaning processes without unduly contributing to a pronounced yield loss in an early manufacturing stage.
摘要翻译：在半导体器件中，通过在形成薄的氮化硅基材料之后将材料暴露于氧等离子体，可以提高氮化钛材料的完整性。氧等离子体可能导致任何微小表面部分的附加钝化，这些微小表面部分可能不被氮化硅基材料适当地覆盖。因此，可以在附加钝化之后进行有效的清洁配方，例如基于SPM的清洁方法，而不会导致氮化钛材料的不适当的材料损失。以这种方式，可以在有效的清洁过程的基础上形成具有非常薄的保护衬垫材料的复杂的高k金属栅极堆叠，而不会在早期制造阶段中过度地造成显着的产量损失。

73. 发明授权

US08455314B2 Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage 有权
标题翻译：晶体管包括高K金属栅极电极结构和嵌入式应变诱导半导体合金，形成于后期阶段
公开(公告)号：US08455314B2
公开(公告)日：2013-06-04
申请号：US13117249
申请日：2011-05-27
申请人： Uwe Griebenow , Jan Hoentschel , Thilo Scheiper , Sven Beyer
发明人： Uwe Griebenow , Jan Hoentschel , Thilo Scheiper , Sven Beyer
IPC分类号： H01L21/8238
CPC分类号： H01L29/7827 , H01L21/28518 , H01L21/76897 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/84 , H01L23/485 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66651 , H01L29/66772 , H01L29/7847 , H01L29/7848 , H01L29/78618 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.
摘要翻译：在复杂的半导体器件中，替代栅极方法可以与用于实现应变诱导半导体材料的工艺策略结合使用，其中应变诱导半导体材料的优越接近和/或替代栅极方法的优异鲁棒性可以通过形成具有优异均匀性的初始栅电极结构，并且在非常先进的制造阶段，即在完成基本晶体管配置之后，提供用于实现应变通道区域的至少一个空腔。

74. 发明申请

US20130126984A1 Patterning of Sensitive Metal-Containing Layers With Superior Mask Material Adhesion by Providing a Modified Surface Layer 审中-公开
标题翻译：通过提供改性表面层，具有优异的掩模材料粘附的敏感金属层的图案化
公开(公告)号：US20130126984A1
公开(公告)日：2013-05-23
申请号：US13301981
申请日：2011-11-22
申请人： Berthold Reimer , Martin Trentzsch , Erwin Grund , Sven Beyer
发明人： Berthold Reimer , Martin Trentzsch , Erwin Grund , Sven Beyer
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L21/28088 , H01L21/02244 , H01L21/0332 , H01L21/31144 , H01L21/32139 , H01L21/76807 , H01L29/4966
摘要： When patterning metal-containing material layers, such as titanium nitride, in critical manufacturing stages, for instance upon forming sophisticated high-k metal gate electrode structures or providing hard mask materials for patterning a metallization system, the surface adhesion of a resist material on the titanium nitride material may be improved by applying a controlled oxidation process.
摘要翻译：当在关键制造阶段中，例如在形成复杂的高k金属栅极电极结构或提供用于图案化金属化系统的硬掩模材料时，将诸如氮化钛的含金属材料层图案化时，抗蚀剂材料在可以通过施加受控氧化工艺来改善氮化钛材料。

75. 发明授权

US08409942B2 Replacement gate approach based on a reverse offset spacer applied prior to work function metal deposition 有权
标题翻译：基于在工作功能金属沉积之前应用的反向偏移间隔件的替换门方法
公开(公告)号：US08409942B2
公开(公告)日：2013-04-02
申请号：US12914570
申请日：2010-10-28
申请人： Thilo Scheiper , Sven Beyer , Uwe Griebenow , Jan Hoentschel
发明人： Thilo Scheiper , Sven Beyer , Uwe Griebenow , Jan Hoentschel
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/28105 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/66553 , H01L29/6659
摘要： In a replacement gate approach, a spacer may be formed in the gate opening after the removal of the placeholder material, thereby providing a superior cross-sectional shape upon forming any electrode metals in the gate opening. Moreover, the spacer may be used for reducing the gate length, while not requiring more complex gate patterning strategies.
摘要翻译：在替代门方法中，在移除占位符材料之后，可以在闸门开口中形成间隔件，从而在门开口中形成任何电极金属时提供优异的横截面形状。此外，间隔物可以用于减小栅极长度，而不需要更复杂的栅极图案化策略。

76. 发明授权

US08378432B2 Maintaining integrity of a high-K gate stack by an offset spacer used to determine an offset of a strain-inducing semiconductor alloy 有权
标题翻译：通过用于确定应变诱导半导体合金的偏移的偏移间隔件来保持高K栅极堆叠的完整性
公开(公告)号：US08378432B2
公开(公告)日：2013-02-19
申请号：US12748992
申请日：2010-03-29
申请人： Richard Carter , Sven Beyer , Martin Trentzsch
发明人： Richard Carter , Sven Beyer , Martin Trentzsch
IPC分类号： H01L21/02 , H01L29/66
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/517 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： In sophisticated transistor elements including a high-k gate metal stack, the integrity of the sensitive gate materials may be ensured by a spacer element that may be concurrently used as an offset spacer for defining a lateral offset of a strain-inducing semiconductor alloy. The cap material of the sophisticated gate stack may be removed without compromising integrity of the offset spacer by providing a sacrificial spacer element. Consequently, an efficient strain-inducing mechanism may be obtained in combination with the provision of a sophisticated gate stack with the required material integrity, while reducing overall process complexity compared to conventional strategies.
摘要翻译：在包括高k栅极金属堆叠的复杂晶体管元件中，敏感栅极材料的完整性可以通过间隔元件来确保，间隔元件可以同时用作用于限定应变诱导半导体合金的横向偏移的偏移间隔物。可以通过提供牺牲间隔元件而不损害偏移间隔物的完整性来移除复杂栅极堆叠的盖材料。因此，与常规策略相比，可以与提供具有所需材料完整性的复杂的栅极叠层相结合，同时降低总体工艺复杂性，可以获得有效的应变诱导机构。

77. 发明申请

US20130034942A1 HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY EARLY CAP LAYER ADAPTATION 有权
标题翻译：高K金属电极结构由早期盖层适应形成
公开(公告)号：US20130034942A1
公开(公告)日：2013-02-07
申请号：US13565970
申请日：2012-08-03
申请人： Rohit Pal , Sven Beyer , Andy Wei , Richard Carter
发明人： Rohit Pal , Sven Beyer , Andy Wei , Richard Carter
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823828
摘要： When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material.
摘要翻译：当在不同导电类型的晶体管中形成高k金属栅极电极结构时，同时在一种类型的晶体管中选择性地并入嵌入式应变诱导半导体合金，可以通过选择性地减小介电帽材料的厚度来实现优异的工艺均匀性栅极层堆叠在不接收应变诱导半导体合金的晶体管的有源区上方。在这种情况下，可以在早期制造阶段中形成复杂的高k金属栅极电极结构的工艺策略中实现优异的限制和因此敏感栅极材料的完整性，而在替代栅极方法中，优良的工艺均匀性是在暴露观察者电极材料的表面时实现。

78. 发明授权

US08357604B2 Work function adjustment in high-k gate stacks for devices of different threshold voltage 有权
标题翻译：用于不同阈值电压的器件的高k栅极堆叠中的功函数调整
公开(公告)号：US08357604B2
公开(公告)日：2013-01-22
申请号：US12905501
申请日：2010-10-15
申请人： Jan Hoentschel , Sven Beyer , Thilo Scheiper
发明人： Jan Hoentschel , Sven Beyer , Thilo Scheiper
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28176 , H01L21/823857 , H01L29/517
摘要： In sophisticated semiconductor devices, different threshold voltage levels for transistors may be set in an early manufacturing stage, i.e., prior to patterning the gate electrode structures, by using multiple diffusion processes and/or gate dielectric materials. In this manner, substantially the same gate layer stacks, i.e., the same electrode materials and the same dielectric cap materials, may be used, thereby providing superior patterning uniformity when applying sophisticated etch strategies.
摘要翻译：在复杂的半导体器件中，可以在早期制造阶段，即在通过使用多个扩散工艺和/或栅极电介质材料图案化栅极电极结构之前，将晶体管的不同阈值电压电平设置。以这种方式，可以使用基本相同的栅极层堆叠，即相同的电极材料和相同的电介质盖材料，从而在应用复杂的蚀刻策略时提供优异的图案均匀性。

79. 发明授权

US08329549B2 Enhancing integrity of a high-k gate stack by protecting a liner at the gate bottom during gate head exposure 失效
标题翻译：通过在栅极头暴露期间保护栅极底部的衬垫，提高高k栅极堆叠的完整性
公开(公告)号：US08329549B2
公开(公告)日：2012-12-11
申请号：US12624672
申请日：2009-11-24
申请人： Sven Beyer , Frank Seliger , Gunter Grasshoff
发明人： Sven Beyer , Frank Seliger , Gunter Grasshoff
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28123 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/4966 , H01L29/517 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： Sophisticated gate stacks including a high-k dielectric material and a metal-containing electrode material may be covered by a protection liner, such as a silicon nitride liner, which may be maintained throughout the entire manufacturing sequence at the bottom of the gate stacks. For this purpose, a mask material may be applied prior to removing cap materials and spacer layers that may be used for encapsulating the gate stacks during the selective epitaxial growth of a strain-inducing semiconductor alloy. Consequently, enhanced integrity may be maintained throughout the entire manufacturing sequence, while at the same time one or more lithography processes may be avoided.
摘要翻译：包括高k电介质材料和含金属的电极材料的复杂的栅极堆叠可以被诸如氮化硅衬垫的保护衬垫覆盖，其可以在栅堆叠的底部的整个制造顺序中保持。为了这个目的，可以在除去在应变诱导半导体合金的选择性外延生长期间可用于封装栅极叠层的覆盖材料和间隔层之前施加掩模材料。因此，可以在整个制造顺序中保持增强的完整性，同时可以避免一个或多个光刻工艺。

80. 发明申请

US20120292671A1 Method of Forming Spacers That Provide Enhanced Protection for Gate Electrode Structures 有权
标题翻译：形成对栅极电极结构提供增强保护的间隔物的方法
公开(公告)号：US20120292671A1
公开(公告)日：2012-11-22
申请号：US13108363
申请日：2011-05-16
申请人： Peter Baars , Sven Beyer , Jan Hoentschel , Thilo Scheiper
发明人： Peter Baars , Sven Beyer , Jan Hoentschel , Thilo Scheiper
IPC分类号： H01L21/3213 , H01L29/78
CPC分类号： H01L29/66772 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/78618 , H01L29/78687
摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a gate electrode structure above a semiconducting substrate and forming a plurality of spacers proximate the gate electrode structures, wherein the plurality of spacers comprises a first silicon nitride spacer positioned adjacent a sidewall of the gate electrode structure, a generally L-shaped silicon nitride spacer positioned adjacent the first silicon nitride spacer, and a silicon dioxide spacer positioned adjacent the generally L-shaped silicon nitride spacer.
摘要翻译：本文公开了形成半导体器件的方法。在一个示例中，该方法包括在半导体衬底之上形成栅电极结构并在栅电极结构附近形成多个间隔区，其中多个间隔物包括邻近栅电极结构的侧壁定位的第一氮化硅间隔区，位于第一氮化硅间隔物附近的通常为L形的氮化硅间隔物，和位于大致L形的氮化硅间隔物附近的二氧化硅隔离物。

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