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    • 76. 发明授权
    • Flash memory device for variably controlling program voltage and method of programming the same
    • 用于可变地控制编程电压的闪存器件及其编程方法
    • US07688631B2
    • 2010-03-30
    • US12171701
    • 2008-07-11
    • Moo-Sung KimSung-Soo Lee
    • Moo-Sung KimSung-Soo Lee
    • G11C11/34G11C16/04
    • G11C16/12
    • Provided is a method of programming the flash memory device including setting increments of program voltages according to data states expressed as threshold voltage distributions of multi-level memory cells. An Increment Step Pulse Programming (ISPP) clock signal corresponds to a loop clock signal and the increments of the program voltages and is generated in response to program pass/fail information. A default level enable signal is generated by performing a counting operation until reaching the increments of the program voltages, in response to the loop clock signal. An additional level enable signal is generated by performing a counting operation until reaching the increments of the program voltages, in response to the ISPP clock signal. The program voltage is increased by 1 increment, in response to the default level enable signal. The program voltage is increased by 2 increments, in response to the additional level enable signal.
    • 提供了一种对闪速存储器件进行编程的方法,包括根据表示为多级存储器单元的阈值电压分布的数据状态来设置编程电压的增量。 增量步进脉冲编程(ISPP)时钟信号对应于环路时钟信号,并且编程电压的增量是响应程序通过/失败信息产生的。 响应于环路时钟信号,通过执行计数操作直到达到编程电压的增量来产生默认电平使能信号。 响应于ISPP时钟信号,通过执行计数操作直到达到编程电压的增量来产生附加电平使能信号。 响应于默认电平使能信号,程序电压增加1个增量。 响应于附加电平使能信号,编程电压增加2个增量。
    • 77. 发明授权
    • Page buffer and multi-state nonvolatile memory device including the same
    • 页面缓冲器和包括其的多状态非易失性存储器件
    • US07675774B2
    • 2010-03-09
    • US12333344
    • 2008-12-12
    • Sung-Soo LeeYoung-Ho LimHyun-Chul ChoDong-Hyuk Chae
    • Sung-Soo LeeYoung-Ho LimHyun-Chul ChoDong-Hyuk Chae
    • G11C16/04
    • G11C16/10G11C11/5628G11C11/5642G11C16/0483G11C2211/5642
    • According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line. The memory device is operable in a read mode which reads the threshold voltage state of the non-volatile memory cells and a programming mode which programs the threshold voltage state of the non-volatile memory cells, wherein the page buffer circuit is selectively responsive to the sub-latch data to inhibit flipping of the logic value of the main latch data in the programming mode.
    • 根据一个方面,存储单元阵列包括连接到多个非易失性存储单元的位线,其中非易失性存储单元可选择性地以至少第一,第二,第三和第四阈值电压状态中的任何一个编程,并且其中 第一,第二,第三和第四阈值电压状态对应于由第一和第二位定义的四个不同的数据值。 页面缓冲电路将逻辑值存储为主锁存数据,并且响应于主锁存信号,以根据位线的电压电平选择性地翻转主锁存数据的逻辑值。 子锁存电路将逻辑值存储为子锁存数据,并且响应于子锁存信号,以根据位线的电压电平选择性地翻转子锁存数据的逻辑值。 存储器件可读取读取非易失性存储器单元的阈值电压状态的读取模式和编程非易失性存储器单元的阈值电压状态的编程模式,其中页面缓冲器电路有选择地响应于 子锁存数据,以禁止在编程模式下翻转主锁存器数据的逻辑值。
    • 79. 发明授权
    • Page-buffer and non-volatile semiconductor memory including page buffer
    • 页缓冲器和非易失性半导体存储器,包括页缓冲器
    • US07379333B2
    • 2008-05-27
    • US11228189
    • 2005-09-19
    • Sung-Soo LeeYoung-Ho LimHyun-Chul ChoDong-Hyuk Chae
    • Sung-Soo LeeYoung-Ho LimHyun-Chul ChoDong-Hyuk Chae
    • G11C11/34
    • G11C16/0483G11C16/26
    • In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.
    • 在一个方面,提供一种可在编程模式和读取模式下操作的非易失性存储器件。 存储器件包括存储单元阵列,其包括多个非易失性存储器单元,多个字线和多个位线。 存储器件还包括用于输出从存储器阵列的位线读取的数据的内部数据输出线以及可操作地连接在存储单元阵列的位线和内部数据输出线之间的页缓冲器。 页面缓冲器包括选择性地连接到位线的感测节点,具有选择性地连接到感测节点的锁存节点的锁存电路,将锁存节点的逻辑电压设置为编程模式的锁存器输入路径,以及 读取模式和与锁存器输入路径分离并根据锁存节点的逻辑电压设置为内部日期输出线的逻辑电压的锁存器输出路径。
    • 80. 发明申请
    • Multi-Color Display Device and Driving Method Thereof
    • 多色显示装置及其驱动方法
    • US20080018798A1
    • 2008-01-24
    • US11781102
    • 2007-07-20
    • Kyong-Tae ParkBeohm-Rock ChoiSung-Soo LeeYoung-Rok SongJi-Hye Choi
    • Kyong-Tae ParkBeohm-Rock ChoiSung-Soo LeeYoung-Rok SongJi-Hye Choi
    • H04N9/73
    • G09G3/3208G09G3/2003G09G2300/0452G09G2320/0271G09G2320/0285G09G2320/0666G09G2340/06
    • A display device and a driving method thereof are provided. The display device includes a plurality of pixels that displays a first color, a second color, a third color, and a white color; a signal processor that generates a white color output image signal based on three input image signals displaying the first to third colors, generates a white color temperature correcting constant based on the white color output image signal, and generates first color, second color, and third color output image signals that correct the first color, second color, and third color input image signals based on the white color temperature correcting constant; and a data driver that converts the output image signal to a data voltage and supplies the data voltage to the pixel to allow the pixel to display an image. Therefore, a color temperature of white light that four color pixels emit can be adjusted to a target color temperature by adjusting an image signal value related to the remaining three color pixels according to luminance of white light that a white pixel emits.
    • 提供了一种显示装置及其驱动方法。 显示装置包括显示第一颜色,第二颜色,第三颜色和白色的多个像素; 基于显示第一至第三颜色的三个输入图像信号产生白色输出图像信号的信号处理器,基于白色输出图像信号生成白色温度校正常数,并生成第一颜色,第二颜色和第三颜色 基于白色温度校正常数校正第一颜色,第二颜色和第三颜色输入图像信号的彩色输出图像信号; 以及将输出图像信号转换为数据电压并将数据电压提供给像素以允许像素显示图像的数据驱动器。 因此,通过根据白色像素发出的白光的亮度调整与剩余的三个像素相关的图像信号值,可以将四色像素发射的白色的色温调整到目标色温。