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71. 发明申请

US20120074520A1 ELECTRICAL FUSE STRUCTURE AND METHOD OF FABRICATING SAME 有权
标题翻译：电熔丝结构及其制造方法
公开(公告)号：US20120074520A1
公开(公告)日：2012-03-29
申请号：US12890941
申请日：2010-09-27
申请人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5256 , H01L21/76805 , H01L21/76807 , H01L21/76831 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved.
摘要翻译：使用位于金属层顶部的双镶嵌结构来提供高编程效率电熔丝。双镶嵌结构包括图案化电介质材料，其具有位于下面的通孔开口上方并连接到下面的通孔开口的线路开口。通孔开口位于顶部并连接到金属层。双镶嵌结构还包括线路开口和通孔开口内的导电特征。电介质间隔物也存在于线路开口和通孔开口内。介电间隔物存在于图案化电介质材料的垂直侧壁上，并将导电特征与图案化电介质材料分开。在线路开口和通孔开口内的电介质间隔物的存在减少了形成导电特征的区域。因此，提供了节省空间的高编程效率电熔丝。

72. 发明申请

US20110018093A1 PROGRAMMABLE ANTI-FUSE STRUCTURE WITH DLC DIELECTRIC LAYER 失效
标题翻译： DLC介电层可编程防结构
公开(公告)号：US20110018093A1
公开(公告)日：2011-01-27
申请号：US12509892
申请日：2009-07-27
申请人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5252 , H01L23/53276 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment an anti-fuse structure is provided that includes a first dielectric material having at least a first anti-fuse region and a second anti-fuse region, wherein at least one of the anti-fuse regions includes a conductive region embedded within the first dielectric material. The anti-fuse structure further includes a first diamond like carbon layer having a first conductivity located on at least the first dielectric material in the first anti-fuse region and a second diamond like carbon layer having a second conductivity located on at least the first dielectric material in the second anti-fuse region. In this embodiment, the second conductivity is different from the first conductivity and the first diamond like carbon layer and the second diamond like carbon layer have the same thickness. The anti-fuse structure also includes a second dielectric material located atop the first and second diamond like carbon layers. The second dielectric material includes at least one conductively filled region embedded therein.
摘要翻译：在一个实施例中，提供了一种抗熔丝结构，其包括具有至少第一抗熔融区域和第二抗熔融区域的第一电介质材料，其中至少一个反熔丝区域包括嵌入在该熔断区域内的导电区域第一电介质材料。反熔丝结构还包括第一金刚石碳层，其具有位于第一抗熔融区域中的至少第一电介质材料上的第一导电性，第二类金刚石碳层具有位于至少第一电介质上的第二导电性材料在第二个反熔丝区域。在本实施例中，第二导电率不同于第一导电性，第一类金刚石碳层和第二类金刚石碳层具有相同的厚度。反熔丝结构还包括位于第一和第二金刚石状碳层顶上的第二电介质材料。第二电介质材料包括嵌入其中的至少一个导电填充区域。

73. 发明申请

US20100264543A1 INTERCONNECT STRUCTURE 有权
标题翻译：互连结构
公开(公告)号：US20100264543A1
公开(公告)日：2010-10-21
申请号：US12424843
申请日：2009-04-16
申请人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76847 , H01L21/76805 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and methods for forming semiconductor interconnect structures are disclosed. In one embodiment, the interconnect structure includes: a substrate including a first liner layer and a first metal layer thereover; a dielectric barrier layer over the first metal layer and the substrate; an inter-level dielectric layer over the dielectric barrier layer; a via extending between the inter-level dielectric layer, the dielectric barrier layer, and the first metal layer, the via including a second liner layer and a second metal layer thereover; and a diffusion barrier layer located between the second liner layer and the first metal layer, wherein a portion of the diffusion barrier layer is located under the dielectric barrier layer.
摘要翻译：公开了用于形成半导体互连结构的互连结构和方法。在一个实施例中，互连结构包括：衬底，其包括第一衬里层和其上的第一金属层; 在所述第一金属层和所述衬底上的介电阻挡层; 电介质阻挡层上的层间电介质层; 所述通孔在所述层间电介质层，所述电介质阻挡层和所述第一金属层之间延伸，所述通孔在其上包括第二衬垫层和第二金属层; 以及位于所述第二衬垫层和所述第一金属层之间的扩散阻挡层，其中所述扩散阻挡层的一部分位于所述电介质阻挡层下方。

74. 发明授权

US08124525B1 Method of forming self-aligned local interconnect and structure formed thereby 失效
标题翻译：形成自对准局部互连和由此形成的结构的方法
公开(公告)号：US08124525B1
公开(公告)日：2012-02-28
申请号：US12913143
申请日：2010-10-27
申请人： Charles W. Koburger, III , David V. Horak , Shom Pomoth , Chih-Chao Yang , Su Chen Fan , Sivananda K. Kanakasabapathy
发明人： Charles W. Koburger, III , David V. Horak , Shom Pomoth , Chih-Chao Yang , Su Chen Fan , Sivananda K. Kanakasabapathy
IPC分类号： H01L21/4763
CPC分类号： H01L21/76885 , H01L21/7682 , H01L21/76895 , H01L21/76897 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention provide a method of forming local interconnect for semiconductor devices. The method includes depositing a blanket layer of conductive material over one or more semiconductor devices; creating a pattern of local interconnect covering a portion of the blanket layer of conductive material; removing rest of the blanket layer of conductive material that is not covered by the pattern of local interconnect; forming the local interconnect by the portion of the blanket layer of conductive material to connect the one or more semiconductor devices.
摘要翻译：本发明的实施例提供一种形成用于半导体器件的局部互连的方法。该方法包括在一个或多个半导体器件上沉积导电材料的覆盖层; 产生覆盖导电材料的覆盖层的一部分的局部互连图案; 去除未被局部互连图案覆盖的导电材料的覆盖层的其余部分; 通过导电材料的覆盖层的部分形成局部互连以连接一个或多个半导体器件。

75. 发明申请

US20110081765A1 METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION 有权
标题翻译：提高生产费用总额的方法
公开(公告)号：US20110081765A1
公开(公告)日：2011-04-07
申请号：US12571483
申请日：2009-10-01
申请人： Jason E. Cummings , Lisa F. Edge , Balasubramanian S. Haran , David V. Horak , Hemanth Jagannathan , Sanjay Mehta
发明人： Jason E. Cummings , Lisa F. Edge , Balasubramanian S. Haran , David V. Horak , Hemanth Jagannathan , Sanjay Mehta
IPC分类号： H01L21/762
CPC分类号： H01L21/76229
摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.
摘要翻译：提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

76. 发明授权

US08623730B2 Method for fabricating silicon-on-insulator transistor with self-aligned borderless source/drain contacts 有权
标题翻译：用于制造具有自对准无边界源极/漏极触点的绝缘体上硅晶体管的方法
公开(公告)号：US08623730B2
公开(公告)日：2014-01-07
申请号：US13617866
申请日：2012-09-14
申请人： Susan S. Fan , Balasubramanian S. Haran , David V. Horak , Charles W. Koburger, III
发明人： Susan S. Fan , Balasubramanian S. Haran , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L21/336
CPC分类号： H01L29/42384 , H01L21/76834 , H01L21/76897 , H01L27/088 , H01L27/1207 , H01L29/4908 , H01L29/66545 , H01L29/78 , H01L29/78651 , H01L29/78654
摘要： A method is provided for fabricating a transistor. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.
摘要翻译：提供了一种用于制造晶体管的方法。在半导体层上形成替代栅极叠层，形成栅极间隔物，形成电介质层。去除虚拟栅极堆叠以形成空腔。在空腔中形成栅极电介质和功函数金属层。空腔填充有栅极导体。门导体和功函数金属层中的仅一个选择性地凹入。在凹部中形成氧化膜，使得其上表面与电介质层的上表面共面。氧化膜用于选择性地生长氧化物盖。形成并蚀刻层间电介质以形成用于源/漏接触的空腔。源极/漏极接触形成在接触腔中，源极/漏极触点的一部分直接位于氧化物盖上。

77. 发明申请

US20120178236A1 METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION 失效
标题翻译：提高生产费用总额的方法
公开(公告)号：US20120178236A1
公开(公告)日：2012-07-12
申请号：US13422138
申请日：2012-03-16
申请人： Jason E. Cummings , Lisa F. Edge , Balasubramanian S. Haran , David V. Horak , Hemanth Jagannathan , Sanjay Mehta
发明人： Jason E. Cummings , Lisa F. Edge , Balasubramanian S. Haran , David V. Horak , Hemanth Jagannathan , Sanjay Mehta
IPC分类号： H01L21/762
CPC分类号： H01L21/76229
摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.
摘要翻译：提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

78. 发明授权

US09105693B2 Microelectronic structure including air gap 有权
标题翻译：微电子结构包括气隙
公开(公告)号：US09105693B2
公开(公告)日：2015-08-11
申请号：US13614563
申请日：2012-09-13
申请人： Daniel C. Edelstein , David V. Horak , Elbert E. Huang , Satyanarayana V. Nitta , Takeshi Nogami , Shom Ponoth , Terry A. Spooner
发明人： Daniel C. Edelstein , David V. Horak , Elbert E. Huang , Satyanarayana V. Nitta , Takeshi Nogami , Shom Ponoth , Terry A. Spooner
IPC分类号： H01L29/40 , H01L21/4763 , H01L21/768
CPC分类号： H05K1/0216 , H01L21/7682 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76852 , H05K1/0298 , H05K1/03 , H05K2201/0707 , H05K2201/09063
摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.
摘要翻译：微电子结构和微电子结构的制造方法提供插入在多个导体层之间的多个空隙。多个空隙也位于衬垫层和层间电介质层之间。空隙提供了微电子结构的增强的电性能。

79. 发明申请

US20120037962A1 SEMICONDUCTOR STRUCTURE HAVING A CONTACT-LEVEL AIR GAP WITHIN THE INTERLAYER DIELECTRICS ABOVE A SEMICONDUCTOR DEVICE AND A METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE USING A SELF-ASSEMBLY APPROACH 有权
标题翻译：在半导体器件之前的中间层电介质中具有接触层空气隙的半导体结构和使用自组装方法形成半导体结构的方法
公开(公告)号：US20120037962A1
公开(公告)日：2012-02-16
申请号：US12854352
申请日：2010-08-11
申请人： Gregory Breyta , David V. Horak , Elbert E. Huang , Charles W. Koburger, III , Douglas C. La Tulipe, JR. , Shom Ponoth
发明人： Gregory Breyta , David V. Horak , Elbert E. Huang , Charles W. Koburger, III , Douglas C. La Tulipe, JR. , Shom Ponoth
IPC分类号： H01L23/48 , H01L21/768 , H01L29/78
CPC分类号： H01L21/7682 , H01L21/31144 , H01L23/4821 , H01L23/485 , H01L23/5222 , H01L23/5329 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device in order to minimize parasitic capacitances (e.g., contact-to-contact capacitance, contact-to-diffusion region capacitance, gate-to-contact capacitance, gate-to-diffusion region capacitance, etc.). Specifically, the structure can comprise a semiconductor device on a substrate and at least three dielectric layers stacked above the semiconductor device. An air gap is positioned with the second dielectric layer aligned above the semiconductor device and extending vertically from the first dielectric layer to the third dielectric layer. Also disclosed are embodiments of a method of forming such a semiconductor structure using a self-assembly approach.
摘要翻译：公开了在半导体器件之上的层间电介质中具有接触电平空气间隙的半导体结构的实施例，以便最小化寄生电容（例如，接触 - 接触电容，接触 - 扩散区电容，栅 - 接触电容，栅极到扩散区域电容等）。具体地，该结构可以包括在衬底上的半导体器件和堆叠在半导体器件上方的至少三个电介质层。定位气隙，其中第二电介质层在半导体器件上方对齐并从第一介电层垂直延伸到第三介质层。还公开了使用自组装方法形成这种半导体结构的方法的实施例。

80. 发明授权

US07943480B2 Sub-lithographic dimensioned air gap formation and related structure 有权
标题翻译：亚光刻尺寸气隙形成及相关结构
公开(公告)号：US07943480B2
公开(公告)日：2011-05-17
申请号：US12029800
申请日：2008-02-12
申请人： Daniel C. Edelstein , Nicholas C. M. Fuller , David V. Horak , Elbert E. Huang , Wai-Kin Li , Anthony D. Lisi , Satyanarayana V. Nitta , Shom Ponoth
发明人： Daniel C. Edelstein , Nicholas C. M. Fuller , David V. Horak , Elbert E. Huang , Wai-Kin Li , Anthony D. Lisi , Satyanarayana V. Nitta , Shom Ponoth
IPC分类号： H01L23/00
CPC分类号： H01L21/7682 , H01L21/0273 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer.
摘要翻译：公开了亚光刻尺寸气隙形成和相关结构。在一个实施例中，一种方法包括在衬底上形成包括互连的介质层; 在电介质层上沉积盖层; 在所述盖层上沉积光致抗蚀剂; 图案化光致抗蚀剂以包括最多部分地覆盖互连的第一沟槽图案; 在所述第一沟槽图案内形成间隔物以形成具有亚光刻尺寸的第二沟槽图案; 将所述第二沟槽图案转移到所述覆盖层中并进入所述互连之间的所述介电层; 并且通过夹住介电层中的沟槽而沉积另一介质层以形成气隙。

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