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71. 发明申请

US20080230821A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20080230821A1
公开(公告)日：2008-09-25
申请号：US12073615
申请日：2008-03-07
申请人： Yutaka Shionoiri
发明人： Yutaka Shionoiri
IPC分类号： H01L27/06
CPC分类号： G06K19/0723 , G06K19/0701 , G06K19/0715
摘要： In a semiconductor device which can perform data communication through wireless communication, to suppress transmission and the like of an AC signal, the semiconductor device includes an input circuit to which a radio signal is input, a first circuit, which generates a constant voltage, such as a constant voltage circuit or a limiter circuit, a second circuit to which the generated constant voltage is input and which can change impedance of the semiconductor device, and a filter provided between the first circuit and the second circuit. Transmission of an AC signal is suppressed by the filter, and malfunctions or operation defects such as complete inoperative due to variation in the constant voltage is prevented.
摘要翻译：在能够通过无线通信进行数据通信的半导体装置中，为了抑制交流信号的发送等，半导体装置具备输入无线信号的输入电路，产生恒定电压的第一电路，作为恒压电路或限幅电路，输入所产生的恒定电压并能够改变半导体器件的阻抗的第二电路以及设置在第一电路和第二电路之间的滤波器。通过滤波器抑制AC信号的传输，并且防止由于恒定电压的变化而导致的故障或诸如完全不工作的操作缺陷。

72. 发明申请

US20080149738A1 Transmitting and receiving circuit and semiconductor device including the same 有权
标题翻译：发射和接收电路和包括其的半导体器件
公开(公告)号：US20080149738A1
公开(公告)日：2008-06-26
申请号：US12003112
申请日：2007-12-20
申请人： Masashi Fujita , Yutaka Shionoiri
发明人： Masashi Fujita , Yutaka Shionoiri
IPC分类号： G06K19/06
CPC分类号： H03F1/56 , H03F1/0205 , H03F3/245 , H03F2200/327
摘要： An object is to provide a circuit configuration with which the number of transistors can be reduced and power conversion efficiency can be prevented from being reduced, in a transmitting and receiving circuit. The transmitting and receiving circuit includes a voltage doubler rectifier circuit having N stages, each of which includes a capacitor, where N is a positive integer. The voltage doubler rectifier circuit having N stages is connected to a circuit having a modulation function. In the capacitor in any one of the N stages, one electrode of the one capacitor is connected to an input terminal of the transmitting and receiving circuit, and a node to which the other electrode of the one capacitor is connected is connected to a circuit having a demodulation function. Since the transmitting and receiving circuit can be formed of fewer transistors, it can be reduced in size. Since a reduction in power conversion efficiency can be prevented, a power supply potential can be efficiently generated.
摘要翻译：目的在于提供一种在发送和接收电路中可以减少晶体管数量并且可以防止功率转换效率降低的电路配置。发送和接收电路包括具有N级的倍压整流电路，每个级包括电容器，其中N是正整数。具有N级的倍压整流电路连接到具有调制功能的电路。在N级中的任何一级的电容器中，一个电容器的一个电极连接到发送和接收电路的输入端子，并且连接一个电容器的另一个电极的节点连接到具有解调功能。由于发送和接收电路可以由更少的晶体管形成，所以可以减小其尺寸。由于可以防止功率转换效率的降低，所以可以有效地产生电源电位。

73. 发明授权

US07362139B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07362139B2
公开(公告)日：2008-04-22
申请号：US11463356
申请日：2006-08-09
申请人： Hiroyuki Miyake , Yutaka Shionoiri
发明人： Hiroyuki Miyake , Yutaka Shionoiri
IPC分类号： H03K19/0175
CPC分类号： H01L27/1255 , G09G3/20 , G09G3/3208 , G09G3/3275 , G09G3/3648 , G09G2300/08 , G09G2310/0218 , G09G2310/0267 , G09G2310/027 , G09G2310/0275 , G09G2310/0286 , G09G2310/0289 , H01L27/1214 , H01L27/3248 , H01L29/78621 , H01L51/5218 , H01L51/5221 , H01L2029/7863 , H01L2251/5315 , H03K19/01714
摘要： A circuit with a large load driving capability, which is structured by single polarity TFTs, is provided. With a capacitor (154) formed between a gate electrode and an output electrode of a TFT (152), the electric potential of the gate electrode of the TFT (152) is increased by a boot strap and normal output with respect to an input signal is obtained without amplitude attenuation of an output signal due to the TFT threshold value. In addition, a capacitor (155) formed between a gate electrode and an output electrode of a TFT (153) compensates for increasing the electric potential of the gate electrode of the TFT (152), and a larger load driving capability is obtained.
摘要翻译：提供了由单极性TFT构成的具有大负载驱动能力的电路。通过形成在TFT（152）的栅电极和输出电极之间的电容器（154），TFT（152）的栅电极的电位通过引导带增加并相对于输入信号的正常输出由于TFT阈值而不产生输出信号的幅度衰减。此外，形成在TFT（153）的栅电极和输出电极之间的电容器（155）补偿增加TFT（152）的栅电极的电位，并且获得更大的负载驱动能力。

74. 发明授权

US07352604B2 Memory and driving method of the same 有权
标题翻译：内存和驱动方法相同
公开(公告)号：US07352604B2
公开(公告)日：2008-04-01
申请号：US11607053
申请日：2006-12-01
申请人： Yutaka Shionoiri , Tomoaki Atsumi , Kiyoshi Kato
发明人： Yutaka Shionoiri , Tomoaki Atsumi , Kiyoshi Kato
IPC分类号： G11C17/00
CPC分类号： G11C7/1096 , G11C7/1078 , G11C7/12 , G11C11/4094 , G11C17/12
摘要： According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.
摘要翻译：根据本发明，通过减少元件的数量来减小安装面积并提高产量，并且提供了对外围电路的负担较小的存储器及其驱动方法。本发明包括一个存储单元，其中存储单元包括位线和字线与插在它们之间的绝缘体交叉的区域中的存储元件，列解码器和包括时钟反相器的选择器。时钟反相器的输入节点连接到位线，而输出节点连接到数据线。在形成时钟反相器的串联连接的多个晶体管中，源极或漏极连接到高电位侧VDD上的电源的P型晶体管的栅极和N型晶体管的栅极源极或漏极连接到低电位侧的电源VSS连接到列解码器。

75. 发明申请

US20060255837A1 Sense Amplifier and Electronic Apparatus Using the Same 有权
公开(公告)号：US20060255837A1
公开(公告)日：2006-11-16
申请号：US11458710
申请日：2006-07-20
申请人： Yutaka Shionoiri , Kiyoshi Kato , Munehiro Azami , Junya Maruyama
发明人： Yutaka Shionoiri , Kiyoshi Kato , Munehiro Azami , Junya Maruyama
IPC分类号： G01R19/00
CPC分类号： H03F3/45179 , G01R19/00 , G11C7/062 , G11C11/4091 , G11C11/413 , G11C2207/063 , H03F3/45183 , H03F3/45188 , H03F2203/45396 , H03F2203/45506 , H03F2203/45546 , H03F2203/45551 , H03F2203/45702 , H03F2203/45726
摘要： A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.

76. 发明申请

US20060192699A1 Serial-to-parallel conversion circuit, and semiconductor display device employing the same 有权
公开(公告)号：US20060192699A1
公开(公告)日：2006-08-31
申请号：US11368640
申请日：2006-05-12
申请人： Munehiro Azami , Mitsuaki Osame , Yutaka Shionoiri , Shou Nagao
发明人： Munehiro Azami , Mitsuaki Osame , Yutaka Shionoiri , Shou Nagao
IPC分类号： H03M9/00
CPC分类号： G09G3/3688 , G09G2310/027 , G09G2310/0286 , G09G2310/0289 , H03M9/00
摘要： In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.

77. 发明授权

US07081774B2 Circuit having source follower and semiconductor device having the circuit 失效
公开(公告)号：US07081774B2
公开(公告)日：2006-07-25
申请号：US10893936
申请日：2004-07-20
申请人： Hiroyuki Miyake , Yutaka Shionoiri
发明人： Hiroyuki Miyake , Yutaka Shionoiri
IPC分类号： H03K19/0175 , H03K19/094 , H03K19/082 , G11C11/14 , G11C11/44
CPC分类号： G09G3/20 , G09G2310/0275 , H03F1/301 , H03F3/505
摘要： When a potential of a power supply line varies according to a flowing current, the gate-source voltage Vgs of a transistor also varies, leading to variations in the constant current between each source follower. In order to solve this problem, a potential Vb of the gate terminal of a transistor as a constant current source is changed in the same manner as a power supply line Vss which is connected to the source terminal of the transistor. Therefore, variations in the constant current are suppressed and variations in the output of the source followers are thus suppressed. In addition, by connecting the circuit having source followers to the output side of a signal line driver circuit, it can be prevented that luminance unevenness of a striped pattern is recognized in a display portion of a semiconductor device.

78. 发明申请

US20050273290A1 Method for evaluating semiconductor device 有权
标题翻译：半导体器件评估方法
公开(公告)号：US20050273290A1
公开(公告)日：2005-12-08
申请号：US11132434
申请日：2005-05-19
申请人： Etsuko Asano , Kiyoshi Kato , Yutaka Shionoiri , Masahiko Hayakawa
发明人： Etsuko Asano , Kiyoshi Kato , Yutaka Shionoiri , Masahiko Hayakawa
IPC分类号： G01R31/317 , G01R31/3187 , G06F19/00
CPC分类号： G01R31/3187 , G01R31/31723 , G01R31/31725 , G01R31/31726
摘要： The present invention provides a method for evaluating an intended element or a parameter. In addition, the invention provides an evaluation method for obtaining a more precise result rapidly. According to the invention, a plurality of evaluation circuits are formed over the same substrate, and while simultaneously operating the plurality of evaluation circuits, an output of one evaluation circuit selected by a selection circuit that is formed over the substrate is arbitrarily evaluated.
摘要翻译：本发明提供了一种用于评估预期元素或参数的方法。此外，本发明提供了一种快速获得更精确结果的评估方法。根据本发明，在相同的基板上形成多个评估电路，并且在同时操作多个评估电路的同时，任意地评估由形成在基板上的选择电路选择的一个评估电路的输出。

79. 发明申请

US20050062515A1 Pulse output circuit, shift register and electronic equipment 有权
标题翻译：脉冲输出电路，移位寄存器和电子设备
公开(公告)号：US20050062515A1
公开(公告)日：2005-03-24
申请号：US10958568
申请日：2004-10-06
申请人： Shou Nagao , Yoshifumi Tanada , Yutaka Shionoiri , Hiroyuki Miyake
发明人： Shou Nagao , Yoshifumi Tanada , Yutaka Shionoiri , Hiroyuki Miyake
IPC分类号： G02F1/1345 , G02F1/133 , G02F1/1368 , G06F1/04 , G09G3/20 , G09G3/36 , G11C19/00 , G11C19/28 , H01L51/50 , H03K3/013 , H03K3/353 , H03K17/00 , H03K17/693 , H03K19/0175 , H03L5/00 , H05B33/14
CPC分类号： G11C19/28 , G09G3/3688 , G09G2310/0275 , G11C19/00
摘要： A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node α is raised. When the potential of the node α reaches (VDD−VthN), the node α becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105. An output at the subsequent stage is then inputted to a TFT 103 to turn the TFT 103 ON, while the potential of the node α of TFTs 102 and 106 is dropped to turn the TFT 105 OFF. As a result, the potential of the output node becomes Low level.
摘要翻译：一种显示装置的驱动电路，其包括单导电类型的TFT并输出具有正常振幅的输出信号。一个脉冲被输入到TFT101和104，使TFT导通，并且提高节点α的电位。当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。因此，随着时钟信号变为高电平，TFT 105导通，输出节点的电位升高。另一方面，随着输出节点的电位升高，由于电容装置107的操作，TFT 105的栅电极的电位进一步上升，使得TFT 105的栅电极的电位变为高于（VDD + VthN）。因此，输出节点的电位升高到VDD，而不会由于TFT 105的阈值电压引起电压降。然后，后级的输出被输入到TFT103，使TFT103导通，同时电位的TFT102和106的节点α的下降以使TFT 105关闭。结果，输出节点的电位变为低电平。

80. 发明授权

US06606045B2 Digital analog converter and electronic device using the same 有权
公开(公告)号：US06606045B2
公开(公告)日：2003-08-12
申请号：US10043306
申请日：2002-01-14
申请人： Munehiro Azami , Mitsuaki Osame , Yutaka Shionoiri , Shou Nagao
发明人： Munehiro Azami , Mitsuaki Osame , Yutaka Shionoiri , Shou Nagao
IPC分类号： H03M166
CPC分类号： G09G3/3275 , G09G3/3233 , G09G3/3648 , G09G3/3688 , G09G2300/0417 , G09G2300/0426 , G09G2300/0842 , G09G2310/027 , G09G2310/0297 , G09G2330/02 , H03M1/0607 , H03M1/68 , H03M1/804
摘要： The present invention relates to a D/A converter circuit which is capable of independently controlling the output voltage amplitude VOUT and the reference voltage. The D/A converter circuit converts “n” bit digital data (“n”: natural number) to analog signals, wherein the respective bits of said “n” bit digital data control a switch, control charge and discharge of electric charges in the capacitance connected to said switch, and output analog signals with the offset potential used as a reference potential.

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