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71. 发明授权

US09090992B2 Method of manufacturing single crystal 有权
标题翻译：单晶制造方法
公开(公告)号：US09090992B2
公开(公告)日：2015-07-28
申请号：US13257742
申请日：2010-11-12
申请人： Taro Nishiguchi , Makoto Sasaki , Shin Harada
发明人： Taro Nishiguchi , Makoto Sasaki , Shin Harada
IPC分类号： C30B29/36 , C30B23/02
CPC分类号： C30B29/36 , C30B23/025
摘要： A seed crystal having a frontside surface and a backside surface is prepared. Surface roughness of the backside surface of the seed crystal is increased. A coating film including carbon is formed on the backside surface of the seed crystal. The coating film and a pedestal are brought into contact with each other with an adhesive interposed therebetween. The adhesive is cured to fix the seed crystal to the pedestal. A single crystal is grown on the seed crystal. Before the growth is performed, a carbon film is formed by carbonizing the coating film.
摘要翻译：准备具有前表面和背面的晶种。晶种背面的表面粗糙度增加。在籽晶的背面形成有包含碳的涂膜。涂膜和基座之间插入有粘合剂，彼此接触。固化粘合剂以将晶种固定到基座。在晶种上生长单晶。在生长之前，通过碳化涂膜形成碳膜。

72. 发明授权

US08872188B2 Silicon carbide semiconductor device and method of manufacturing thereof 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US08872188B2
公开(公告)日：2014-10-28
申请号：US13501373
申请日：2010-01-19
申请人： Misako Honaga , Shin Harada
发明人： Misako Honaga , Shin Harada
IPC分类号： H01L29/12 , H01L29/78 , H01L21/3105 , H01L29/04 , H01L29/66 , H01L21/04 , H01L29/16 , H01L21/02 , H01L29/06
CPC分类号： H01L29/7802 , H01L21/02378 , H01L21/02433 , H01L21/02529 , H01L21/02609 , H01L21/049 , H01L29/045 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/78
摘要： A silicon carbide semiconductor device is provided that includes a semiconductor layer made of silicon carbide and having a surface tilted at an angle in a range of not less than 50° and not more than 65° relative to the {0001} plane, and an insulating film formed to contact the surface of the semiconductor layer. A maximum value of the nitrogen concentration in a region within 10 nm from the interface between the semiconductor layer and the insulating film is not less than 1×1021 cm−3, and the semiconductor device has a channel direction in a range of ±10° relative to the direction orthogonal to the direction in the surface of the semiconductor layer. A method of manufacturing the silicon carbide semiconductor device is also provided.
摘要翻译：提供一种碳化硅半导体器件，其包括由碳化硅制成的半导体层，并且具有相对于{0001}面在不小于50°且不超过65°的范围内倾斜的表面，并且绝缘形成为与半导体层的表面接触的膜。半导体层与绝缘膜之间的界面10nm以内的氮浓度的最大值不小于1×1021cm-3，半导体器件的通道方向在±10°的范围内相对于在半导体层的表面中与<-2110>方向正交的方向。还提供了制造碳化硅半导体器件的方法。

73. 发明授权

US08686434B2 Silicon carbide semiconductor device and method for manufacturing the same 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US08686434B2
公开(公告)日：2014-04-01
申请号：US13063083
申请日：2009-02-03
申请人： Shin Harada , Takeyoshi Masuda , Keiji Wada , Masato Tsumori
发明人： Shin Harada , Takeyoshi Masuda , Keiji Wada , Masato Tsumori
IPC分类号： H01L29/06
CPC分类号： H01L29/1608 , H01L21/02378 , H01L21/02433 , H01L21/02447 , H01L21/02529 , H01L21/3003 , H01L21/324 , H01L29/045 , H01L29/0878 , H01L29/36 , H01L29/6606 , H01L29/66068 , H01L29/7802 , H01L29/94
摘要： There is provided a silicon carbide semiconductor device having excellent electrical characteristics such as channel mobility, and a method for manufacturing the same. A semiconductor device includes a substrate made of silicon carbide and having an off-angle of greater than or equal to 50° and less than or equal to 65° with respect to a surface orientation of {0001}, a p-type layer serving as a semiconductor layer, and an oxide film serving as an insulating film. The p-type layer is formed on the substrate and is made of silicon carbide. The oxide film is formed to contact with a surface of the p-type layer. A maximum value of the concentration of nitrogen atoms in a region within 10 nm of an interface between the semiconductor layer and the insulating film (interface between a channel region and the oxide film) is greater than or equal to 1×1021 cm−3.
摘要翻译：提供了具有优异的电特性如沟道迁移率的碳化硅半导体器件及其制造方法。半导体器件包括相对于{0001}的表面取向具有大于或等于50°且小于或等于65°的偏角度的碳化硅制成的衬底，用作半导体层和用作绝缘膜的氧化膜。 p型层形成在基板上，由碳化硅制成。氧化膜形成为与p型层的表面接触。半导体层与绝缘膜（沟道区域和氧化物膜之间的界面）的界面的10nm以内的区域的氮原子的浓度的最大值为1×1021cm-3以上。

74. 发明授权

US08643065B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08643065B2
公开(公告)日：2014-02-04
申请号：US12919992
申请日：2009-12-11
申请人： Kazuhiro Fujikawa , Hideto Tamaso , Shin Harada , Yasuo Namikawa
发明人： Kazuhiro Fujikawa , Hideto Tamaso , Shin Harada , Yasuo Namikawa
IPC分类号： H01L29/80
CPC分类号： H01L29/66068 , H01L21/0465 , H01L29/1066 , H01L29/1608 , H01L29/8083
摘要： A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w1) in the direction along the upper surface greater than a width (w2) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.
摘要翻译： JFET是半导体器件，允许更可靠地实现通过使用SiC作为材料而基本上可实现的特性，并且包括至少由碳化硅制成的上表面的晶片和形成在上表面上的栅极接触电极。晶片包括用作离子注入区域的第一p型区域，其形成为包括上表面。第一p型区域包括设置成包括上表面的基极区域和突出区域。基部区域沿着上表面的方向具有大于突出区域的宽度（w2）的宽度（w1）。栅极接触电极设置成与第一p型区域接触，使得栅极接触电极完全位于第一p型区域上，如平面图所示。

75. 发明授权

US08536583B2 MOSFET and method for manufacturing MOSFET 有权
标题翻译： MOSFET和MOSFET制造方法
公开(公告)号：US08536583B2
公开(公告)日：2013-09-17
申请号：US13063298
申请日：2010-03-23
申请人： Keiji Wada , Shin Harada , Takeyoshi Masuda , Misako Honaga
发明人： Keiji Wada , Shin Harada , Takeyoshi Masuda , Misako Honaga
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： H01L29/7802 , H01L29/045 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/78 , H01L29/94
摘要： A MOSFET includes: a silicon carbide (SiC) substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a semiconductor layer formed on the main surface of the SiC substrate; and an insulating film formed in contact with a surface of the semiconductor layer. The MOSFET has a sub-threshold slope of not more than 0.4 V/Decade.
摘要翻译： MOSFET包括：碳化硅（SiC）基板，其具有相对于{0001}面具有不小于50°且不大于65°的偏离角的主表面; 形成在所述SiC衬底的主表面上的半导体层; 以及与半导体层的表面接触形成的绝缘膜。 MOSFET的子阈值斜率不超过0.4 V /十年。

76. 发明授权

US08525187B2 Insulated gate bipolar transistor 有权
标题翻译：绝缘栅双极晶体管
公开(公告)号：US08525187B2
公开(公告)日：2013-09-03
申请号：US13122353
申请日：2010-03-23
申请人： Shin Harada , Keiji Wada , Toru Hiyoshi
发明人： Shin Harada , Keiji Wada , Toru Hiyoshi
IPC分类号： H01L29/15
CPC分类号： H01L29/7395 , H01L29/045 , H01L29/1608 , H01L29/66068 , H01L29/78
摘要： An IGBT, which is capable of reducing on resistance by reducing channel mobility, includes: an n type substrate made of SiC and having a main surface with an off angle of not less than 50° and not more than 65° relative to a plane orientation of {0001}; a p type reverse breakdown voltage holding layer made of SiC and formed on the main surface of the substrate; an n type well region formed to include a second main surface of the reverse breakdown voltage holding layer; an emitter region formed in the well region to include the second main surface and including a p type impurity at a concentration higher than that of the reverse breakdown voltage holding layer; a gate oxide film formed on the reverse breakdown voltage holding layer; and a gate electrode formed on the gate oxide film. In a region including an interface between the well region and the gate oxide film, a high-concentration nitrogen region is formed to have a nitrogen concentration higher than those of the well region and the gate oxide film.
摘要翻译：能够通过降低沟道迁移率而降低导通电阻的IGBT包括：由SiC制成的n型衬底，其主表面相对于平面取向具有不小于50度且不大于65度的偏离角 {0001}; 由SiC制成的p型反向击穿电压保持层，形成在基板的主表面上; 形成为包括反向击穿电压保持层的第二主表面的n型阱区; 在所述阱区域中形成的包括所述第二主表面并且包含浓度高于所述反向击穿电压保持层的p型杂质的发射极区域; 形成在反向击穿电压保持层上的栅极氧化膜; 以及形成在栅氧化膜上的栅电极。在包括阱区和栅极氧化膜之间的界面的区域中，形成高浓度氮区，使得氮浓度高于阱区和栅极氧化膜的氮浓度。

77. 发明授权

US08502236B2 Insulated gate field effect transistor 有权
标题翻译：绝缘栅场效应晶体管
公开(公告)号：US08502236B2
公开(公告)日：2013-08-06
申请号：US13122377
申请日：2010-03-23
申请人： Shin Harada , Keiji Wada , Toru Hiyoshi
发明人： Shin Harada , Keiji Wada , Toru Hiyoshi
IPC分类号： H01L29/15
CPC分类号： H01L29/7828 , H01L21/049 , H01L29/045 , H01L29/1608 , H01L29/518 , H01L29/66068 , H01L29/7838 , H01L2924/0002 , H01L2924/00
摘要： A MOSFET, which is capable of reducing on resistance by reducing channel mobility even when a gate voltage is high, includes: an n type substrate made of SiC and having a main surface with an off angle of 50°-65° relative to a {0001} plane; an n type reverse breakdown voltage holding layer made of SiC and formed on the main surface of the substrate; a p type well region formed in the reverse breakdown voltage holding layer distant away from a first main surface thereof; a gate oxide film formed on the well region; an n type contact region disposed between the well region and the gate oxide film; a channel region connecting the n type contact region and the reverse breakdown voltage holding layer; and a gate electrode disposed on the gate oxide film. In a region including an interface between the channel region and the gate oxide film, a high-concentration nitrogen region is formed.
摘要翻译：即使栅极电压高，通过降低沟道迁移能力也能够降低导通电阻的MOSFET包括：由SiC制成的n型衬底，其主表面相对于{ 0001}平面; 由SiC制成的n型反向击穿电压保持层，形成在基板的主表面上; 形成在远离其第一主表面的反向击穿电压保持层中的p型阱区; 形成在所述阱区上的栅氧化膜; 设置在所述阱区域和所述栅氧化膜之间的n型接触区域; 连接n型接触区域和反向击穿电压保持层的沟道区域; 以及设置在栅氧化膜上的栅电极。在包括沟道区域和栅极氧化膜之间的界面的区域中，形成高浓度氮区域。

78. 发明授权

US08450750B2 Silicon carbide semiconductor device and method of manufacturing thereof 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US08450750B2
公开(公告)日：2013-05-28
申请号：US13130986
申请日：2010-01-27
申请人： Misako Honaga , Shin Harada
发明人： Misako Honaga , Shin Harada
IPC分类号： H01L29/15
CPC分类号： H01L21/28008 , H01L21/049 , H01L29/045 , H01L29/1608 , H01L29/518 , H01L29/66068 , H01L29/7813
摘要： A silicon carbide semiconductor device is provided that includes a semiconductor layer made of silicon carbide and having a surface with a trench having a sidewall formed of a crystal plane tilted at an angle in a range of not less than 50° and not more than 65° relative to the {0001} plane, and an insulating film formed to contact the sidewall of the trench. A maximum value of the nitrogen concentration in a region within 10 nm from the interface between the sidewall of the trench and the insulating film is not less than 1×1021 cm−3, and the semiconductor device has a channel direction in a range of ±10° relative to the direction orthogonal to the direction in the sidewall of the trench. A method of manufacturing the silicon carbide semiconductor device is also provided.
摘要翻译：提供一种碳化硅半导体器件，其包括由碳化硅制成的半导体层，并具有具有沟槽的表面，所述沟槽具有由以不小于50°且不大于65°的范围内倾斜的晶体面形成的侧壁相对于{0001}面，以及形成为与沟槽的侧壁接触的绝缘膜。与沟槽侧壁和绝缘膜之间的界面10nm以内的区域的氮浓度的最大值不小于1×1021cm-3，半导体器件的沟道方向在± 相对于沟槽侧壁中与<-2110>方向垂直的方向为10°。还提供了制造碳化硅半导体器件的方法。

79. 发明申请

US20130056752A1 SILICON CARBIDE SUBSTRATE, SILICON CARBIDE SUBSTRATE MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 审中-公开
标题翻译：硅碳化硅基板，碳化硅基板制造方法和半导体器件制造方法
公开(公告)号：US20130056752A1
公开(公告)日：2013-03-07
申请号：US13599278
申请日：2012-08-30
申请人： Shinsuke Fujiwara , Shin Harada
发明人： Shinsuke Fujiwara , Shin Harada
IPC分类号： H01L29/38 , H01L21/78
CPC分类号： H01L29/1608 , H01L21/02002 , H01L21/02439 , H01L21/02494 , H01L21/02516 , H01L21/02529 , H01L21/02609 , H01L21/02658 , H01L21/046 , H01L21/049 , H01L29/045 , H01L29/66068 , H01L29/7802
摘要： An edge region has a width of 5 mm. A valid region is surrounded by the edge region, and has an area greater than or equal to 100 cm2. At the valid region, a micropipe having a cross-sectional area exceeding 1 μm2 is not present. The valid region includes a plurality of high-quality regions occupying 70% or more of the valid region. Each of the plurality of high-quality regions has a square shape, an area greater than or equal to 1 cm2, and a micropipe density less than or equal to 1 micropipe per 1 cm2.
摘要翻译：边缘区域的宽度为5mm。有效区域由边缘区域包围，并且具有大于或等于100cm 2的面积。在有效区域，不存在横截面积超过1μm2的微管。有效区域包括占有效区域的70％以上的多个高质量区域。多个高质量区域中的每一个具有正方形形状，大于或等于1cm 2的面积，以及每1cm2小于或等于1个微管的微管密度。

80. 发明申请

US20120171850A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20120171850A1
公开(公告)日：2012-07-05
申请号：US13394770
申请日：2010-08-24
申请人： Misako Honaga , Takeyoshi Masuda , Shin Harada
发明人： Misako Honaga , Takeyoshi Masuda , Shin Harada
IPC分类号： H01L21/311
CPC分类号： H01L29/7802 , H01L23/544 , H01L29/1608 , H01L29/66068 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes the steps of forming a semiconductor layer made of SiC on an SiC substrate, forming a film on the semiconductor layer, and forming a groove in the film. The semiconductor device including a chip having an interlayer insulating film includes a groove formed in the interlayer insulating film to cross the chip.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在SiC衬底上形成由SiC制成的半导体层，在半导体层上形成膜，并在膜中形成沟槽。包括具有层间绝缘膜的芯片的半导体器件包括形成在层间绝缘膜中以跨越芯片的沟槽。

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