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71. 发明授权

US07155574B2 Look ahead LRU array update scheme to minimize clobber in sequentially accessed memory 失效
标题翻译：展望未来的LRU阵列更新方案，以最大限度地减少顺序存取的内存中的破坏
公开(公告)号：US07155574B2
公开(公告)日：2006-12-26
申请号：US11414541
申请日：2006-05-01
申请人： Peter J. Smith , Satish K. Damaraju , Subramaniam Maiyuran
发明人： Peter J. Smith , Satish K. Damaraju , Subramaniam Maiyuran
IPC分类号： G06F12/00
CPC分类号： G06F9/3808 , G06F12/123 , G06F12/127
摘要： A high-speed memory management technique that minimizes clobber in sequentially accessed memory, including but not limited to, for example, a trace cache. The method includes selecting a victim set from a sequentially accessed memory; selecting a victim way for the selected victim set; reading a next way pointer from a trace line of a trace currently stored in the selected victim way, if the selected victim way has the next way pointer; and writing a next line of the new trace into the selected victim way over the trace line of the currently stored trace. The method also includes forcing a replacement algorithm of next set to select a victim way of the next set using the next way pointer, if the trace line of the currently stored trace is not an active trace tail line.
摘要翻译：一种高速存储器管理技术，其使顺序访问的存储器中的电路最小化，包括但不限于例如跟踪高速缓存。该方法包括从顺序访问的存储器中选择一个受害者集合; 选择所选受害者集合的受害方式; 如果所选择的受害者方式具有下一个方向指针，则从当前存储在所选择的受害者方式中的跟踪的跟踪行读取下一个方向指针; 并通过当前存储的轨迹的轨迹线将新轨迹的下一行写入所选的受害者方式。该方法还包括，如果当前存储的跟踪的跟踪线不是活动跟踪尾线，则使用下一个方向指针强制下一集合的替换算法来选择下一集合的受害方式。

72. 发明授权

US06842180B1 Opportunistic sharing of graphics resources to enhance CPU performance in an integrated microprocessor 有权
标题翻译：图形资源的机会共享，以增强集成微处理器中的CPU性能
公开(公告)号：US06842180B1
公开(公告)日：2005-01-11
申请号：US09665923
申请日：2000-09-20
申请人： Subramaniam Maiyuran , Vivek Garg , Jagannath Keshava , Salvador Palanca
发明人： Subramaniam Maiyuran , Vivek Garg , Jagannath Keshava , Salvador Palanca
IPC分类号： G06F12/08 , G06F15/167
CPC分类号： G09G5/001 , G06F12/0862 , G06F12/0897 , G06F2212/6022 , G06F2212/6026 , G09G5/363 , G09G5/39
摘要： An electronic device that has an integrated central processing unit (CPU) including a pre-fetch stride analyzer and an out-of-order engine is provided. The electronic device also has a graphics engine, having graphics memory, that is coupled to the integrated CPU. A main memory that is coupled to a memory controller is provided. The memory controller is also coupled to the CPU and the graphics engine. The device has a host address decoder coupled to the integrated CPU. A front side bus (FSB) is provided that is coupled to the integrated CPU and the host address decoder. Also provided is a plurality of memory components. Accordingly, either the plurality of memory components or the graphics memory can be shared to perform alternate memory functions. Additionally, a method is provided that determines allocation availability between memory components in an integrated computer processing unit. The method also shares an available memory component as a pre-fetch buffer and another available memory component as a victim cache.
摘要翻译：提供具有集成中央处理单元（CPU）的电子设备，其包括预取步幅分析器和无序引擎。电子设备还具有连接到集成CPU的具有图形存储器的图形引擎。提供耦合到存储器控制器的主存储器。存储器控制器还耦合到CPU和图形引擎。该设备具有耦合到集成CPU的主机地址解码器。提供了前置总线（FSB），其耦合到集成CPU和主机地址解码器。还提供了多个存储器组件。因此，可以共享多个存储器组件或图形存储器以执行备用存储器功能。此外，提供了一种确定集成计算机处理单元中的存储器组件之间的分配可用性的方法。该方法还将可用存储器组件作为预取缓冲区和另一可用存储器组件共享作为受害缓存。

73. 发明授权

US06772291B2 Method and apparatus for cache replacement for a multiple variable-way associative cache 失效
标题翻译：用于多个可变方式关联高速缓存的高速缓存替换的方法和装置
公开(公告)号：US06772291B2
公开(公告)日：2004-08-03
申请号：US10206748
申请日：2002-07-26
申请人： Salvador Palanca , Subramaniam Maiyuran
发明人： Salvador Palanca , Subramaniam Maiyuran
IPC分类号： G06F1212
CPC分类号： G06F12/0848 , G06F12/123
摘要： A method and apparatus for cache replacement in a multiple variable-way associative cache is disclosed. The method according to the present techniques partitions a cache array dynamically based upon requests for memory from an integrated device having a plurality of processors.
摘要翻译：公开了一种用于多可变方式关联高速缓存中的高速缓存替换的方法和装置。根据本技术的方法基于来自具有多个处理器的集成设备对存储器的请求而动态地划分高速缓存阵列。

74. 发明授权

US06546462B1 CLFLUSH micro-architectural implementation method and system 有权
标题翻译： CLFLUSH微架构实现方法和系统
公开(公告)号：US06546462B1
公开(公告)日：2003-04-08
申请号：US09475759
申请日：1999-12-30
申请人： Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran
发明人： Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran
IPC分类号： G06F1200
CPC分类号： G06F12/0811 , G06F12/0804
摘要： A system and method for flushing a cache line associated with a linear memory address from all caches in the coherency domain. A cache controller receives a memory address, and determines whether the memory address is stored within the closest cache memory in the coherency domain. If a cache line stores the memory address, it is flushed from the cache. The flush instruction is allocated to a write-combining buffer within the cache controller. The write-combining buffer transmits the information to the bus controller. The bus controller locates instances of the memory address stored within external and intel cache memories within the coherency domain; these instances are flushed. The flush instruction can then be evicted from the write-combining buffer. Control bits may be used to indicate whether a write-combining buffer is allocated to the flush instruction, whether the memory address is stored within the closest cache memory, and whether the flush instruction should be evicted from the write-combining buffer.
摘要翻译：一种用于从一致性域中的所有高速缓存中刷新与线性存储器地址相关联的高速缓存行的系统和方法。高速缓存控制器接收存储器地址，并且确定存储器地址是否存储在相干域中最接近的高速缓冲存储器中。如果缓存行存储内存地址，则从缓存中刷新。刷新指令被分配给高速缓存控制器内的写入组合缓冲器。写合成缓冲器将信息发送到总线控制器。总线控制器定位存储在相干域内的外部和英特尔高速缓存存储器中的存储器地址的实例; 这些实例被刷新。然后可以从写入组合缓冲器中逐出驱动刷新指令。控制位可以用于指示是否将写入组合缓冲器分配给闪存指令，存储器地址是否存储在最接近的高速缓冲存储器中，以及是否应该从写入组合缓冲器中驱逐刷新指令。

75. 发明授权

US06526499B2 Method and apparatus for load buffers 失效
标题翻译：负载缓冲器的方法和装置
公开(公告)号：US06526499B2
公开(公告)日：2003-02-25
申请号：US09758486
申请日：2001-01-10
申请人： Salvador Palanca , Shekoufeh Qawami , Niranjan L. Cooray , Angad Narang , Subramaniam Maiyuran
发明人： Salvador Palanca , Shekoufeh Qawami , Niranjan L. Cooray , Angad Narang , Subramaniam Maiyuran
IPC分类号： G06F930
CPC分类号： G06F9/3857 , G06F9/30047 , G06F9/3824 , G06F9/3834 , G06F13/1668
摘要： The present invention discloses a method and apparatus for implementing a senior load instruction type. An instruction requesting a memory reference is decoded. The decoded instruction is then dispatched to a memory ordering unit. The instruction is retired from a load buffer and is executed after retiring.
摘要翻译：本发明公开了一种实现高级加载指令类型的方法和装置。解码请求存储器参考的指令。然后将解码的指令分派到存储器订购单元。该指令从加载缓冲区中退出，并在退出后执行。

76. 发明授权

US06356115B1 Charge sharing and charge recycling for an on-chip bus 有权
公开(公告)号：US06356115B1
公开(公告)日：2002-03-12
申请号：US09368639
申请日：1999-08-04
申请人： Sanjay Dabral , Ming Zeng , Subramaniam Maiyuran
发明人： Sanjay Dabral , Ming Zeng , Subramaniam Maiyuran
IPC分类号： H03K19094
CPC分类号： G11C7/106 , G06F13/4077 , G11C7/1051 , G11C7/1078 , G11C7/1087 , H03K19/01855 , Y02D10/14 , Y02D10/151
摘要： A method for charge sharing among data conductors of a bus. The bus has a first data conductor and a corresponding data conductor. The method includes detecting the logic levels on the first data conductor and the corresponding data conductor, and generating a charge sharing signal for sharing charge between the first data conductor and the corresponding data conductor.

77. 发明授权

US06205520B1 Method and apparatus for implementing non-temporal stores 失效
标题翻译：用于实施非时间存储的方法和装置
公开(公告)号：US06205520B1
公开(公告)日：2001-03-20
申请号：US09053387
申请日：1998-03-31
申请人： Salvador Palanca , Vladimir Pentkovski , Steve Tsai , Subramaniam Maiyuran
发明人： Salvador Palanca , Vladimir Pentkovski , Steve Tsai , Subramaniam Maiyuran
IPC分类号： G06F1200
CPC分类号： G06F9/3824 , G06F9/3842 , G06F12/0804 , G06F12/0888 , G06F12/0897
摘要： A processor is disclosed. The processor includes a decoder to decode instructions and a circuit, in response to a decoded instruction, detects an incoming write back or write through streaming store instruction that misses a cache and allocates a buffer in write combining mode. The circuit, in response to a second decoded instruction, detects either an uncacheable speculative write combining store instruction or a second write back streaming store or write through streaming store instruction that hits the buffer and merges the second decoded instruction with the buffer.
摘要翻译：公开了一种处理器。处理器包括解码器，用于对指令和电路进行解码，响应于解码的指令，通过错过高速缓冲存储器的流存储指令检测进入写回或写入，并以写入合并模式分配缓冲器。响应于第二解码指令，该电路检测不可缓存的推测写入组合存储指令或第二回写流存储器，或通过命中缓冲器的流存储指令进行写入，并将第二解码指令与缓冲器合并。

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