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71. 发明授权

US06893949B2 Semiconductor devices having contact plugs and local interconnects and methods for making the same 有权
标题翻译：具有接触插头和局部互连的半导体器件及其制造方法
公开(公告)号：US06893949B2
公开(公告)日：2005-05-17
申请号：US10696165
申请日：2003-10-28
申请人： Sanh D. Tang , Daniel Smith , Jason Taylor
发明人： Sanh D. Tang , Daniel Smith , Jason Taylor
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8242 , H01L21/8244 , H01L23/485 , H01L23/522 , H01L21/3205 , H01L21/4763 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L27/10855 , H01L21/76831 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L23/522 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/11 , H01L2924/0002 , H01L2924/00
摘要： Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are completely covered by an insulating cap) is provided. An insulating layer overlying the transistors and the active areas is deposited, where upon a hard mask is created and patterned to form a contact plug/interconnect opening over a first active area and a portion of a first transistor immediately adjacent the first active area. A spacer is formed within the contact plug/interconnect opening. Insulating material overlying active areas between transistors is removed. A portion of the gate region of the first transistor is then exposed and interconnect material is deposited within the contact plug/interconnect opening onto the exposed portion of the gate region of the first transistor and the first active area.
摘要翻译：例如，提供了一种用于制造半导体器件中的电互连的方法，其中包括具有栅极区域的两个或更多个晶体管的衬底，其中栅极区域不被暴露（例如，栅极区域被绝缘盖完全覆盖）提供。沉积覆盖晶体管和有源区的绝缘层，其中在形成硬掩模并图案化之后，形成紧邻第一有源区的第一有源区和第一晶体管的一部分的接触插塞/互连开口。隔离件形成在接触插头/互连开口内。除去晶体管之间覆盖有源区域的绝缘材料。然后第一晶体管的栅极区域的一部分被暴露，并且互连材料沉积在接触插头/互连开口内，到第一晶体管和第一有源区域的栅极区域的暴露部分上。

72. 发明授权

US06636415B2 Capacitor constructions, methods of forming bitlines, and methods of forming capacitor and bitline structures 有权
公开(公告)号：US06636415B2
公开(公告)日：2003-10-21
申请号：US10198401
申请日：2002-07-17
申请人： Sanh D. Tang , Raj Narasimhan
发明人： Sanh D. Tang , Raj Narasimhan
IPC分类号： H01K4005
CPC分类号： H01L27/10855 , H01L21/76897 , H01L27/10885
摘要： The invention encompasses a method of forming bitlines. A substrate is provided, and comprises a plurality of spaced electrical nodes. A bitline layer is formed over at least some of the spaced electrical nodes. The bitline layer comprises at least one conductive material. Openings are etched through the bitline layer and to the electrical nodes. After the openings are formed, the bitline layer is patterned into bitlines. The invention also encompasses a method of forming a capacitor and bitline structure. A substrate is provided, and comprises a plurality of spaced electrical nodes. A stack of bitline materials is formed over at least some of the spaced electrical nodes. The bitline materials comprise at least one insulative material over at least one conductive material. Openings are etched through the bit line materials and to the electrical nodes. Conductive masses are formed in at least some of the openings. After the conductive masses are formed, the bitline materials are patterned into bitlines. Capacitor constructions are formed over the patterned bit lines and electrically connected to the electrical nodes through the conductive masses. Additionally, the invention encompasses capacitor constructions.

73. 发明授权

US06507064B1 Double sided container capacitor for DRAM cell array and method of forming same 有权
公开(公告)号：US06507064B1
公开(公告)日：2003-01-14
申请号：US09569570
申请日：2000-05-10
申请人： Sanh D. Tang , Robert J. Burke
发明人： Sanh D. Tang , Robert J. Burke
IPC分类号： H01L27108
CPC分类号： H01L27/10888 , H01L27/10811 , H01L28/84 , H01L28/91
摘要： An apparatus and method is presented for a DRAM memory cell array exhibiting improved alignment tolerance for bit line contact formation and utilizing closely-spaced double-sided stacked capacitors for increased overall feature density on the circuit die. The use of a sacrificial insulating layer, an etch-stop insulating layer, and insulating spacers surrounding the bit line contact plug permits wet etching of the sacrificial layer to enable double-sided capacitors to be formed close together. In the resulting structure, only the bit line contact plug and insulating sidewall spacers separates adjacent capacitors and hence DRAM cells can be more tightly packed on the circuit die. Another aspect of the invention is improved alignment tolerance of the bit line contact plug. Because the bit line contact plug is formed prior to the double-sided capacitors, and then the double sided capacitors are formed to occupy all of the space laterally surrounding the bit line contact plug and its insulating spacers, mask alignment errors are less likely to affect this arrangement.

74. 发明授权

US06376380B1 Method of forming memory circuitry and method of forming memory circuitry comprising a buried bit line array of memory cells 有权
标题翻译：形成存储器电路的方法和形成存储器电路的方法，所述存储器电路包括存储器单元的掩埋位线阵列
公开(公告)号：US06376380B1
公开(公告)日：2002-04-23
申请号：US09652601
申请日：2000-08-30
申请人： Sanh D. Tang , Raj Narasimhan
发明人： Sanh D. Tang , Raj Narasimhan
IPC分类号： H01L2100
CPC分类号： H01L27/10885 , H01L21/3212 , H01L21/76816 , H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10888
摘要： The invention includes methods of forming memory circuitry, including methods of forming memory circuitry comprising a buried bit line array of memory cells. In one implementation, a method of forming memory circuitry comprising a buried bit line array of memory cells includes, in a single planarizing step, planarizing storage node contact opening plugging material and bit line trench plugging material to insulating material to form bit lines and storage node contacts which are electrically isolated laterally from one another by the insulating material. In one implementation, a method of forming memory circuitry comprising a buried bit line array of memory cells, includes forming word lines over a semiconductor substrate. An insulating layer is formed over the substrate and over the word lines. Using a single photomasking step, bit line contact openings and capacitor storage node contact openings are patterned and formed into the insulating layer. After forming the bit line contact openings and the storage node contact openings, bit line trenches are formed into the insulating layer and which overlie and connect with the bit line contact openings.
摘要翻译：本发明包括形成存储器电路的方法，包括形成包括存储器单元的掩埋位线阵列的存储器电路的方法。在一个实现中，形成存储器电路的方法包括存储单元的掩埋位线阵列，在单个平面化步骤中，将存储节点接触开口堵塞材料和位线沟槽封堵材料平坦化成绝缘材料以形成位线和存储节点通过绝缘材料彼此横向电绝缘的触点。在一个实施方式中，一种形成包括存储器单元的掩埋位线阵列的存储器电路的方法包括在半导体衬底上形成字线。绝缘层形成在衬底上和字线之上。使用单个光掩模步骤，将位线接触开口和电容器存储节点接触开口图案化并形成为绝缘层。在形成位线接触开口和存储节点接触开口之后，位线沟槽形成为绝缘层，并且覆盖并与位线接触开口连接。

75. 发明申请

US20220302317A1 MEMORY DEVICES INCLUDING VOID SPACES BETWEEN TRANSISTOR FEATURES, AND RELATED SEMICONDUCTOR DEVICES AND ELECTRONIC SYSTEMS 有权
公开(公告)号：US20220302317A1
公开(公告)日：2022-09-22
申请号：US17301793
申请日：2021-04-14
申请人： Kamal M. Karda , Ramanathan Gandhi , Hong Li , Haitao Liu , Durai Vishak Nirmal Ramaswamy , Sanh D. Tang , Scott E. Sills
发明人： Kamal M. Karda , Ramanathan Gandhi , Hong Li , Haitao Liu , Durai Vishak Nirmal Ramaswamy , Sanh D. Tang , Scott E. Sills
IPC分类号： H01L29/786 , H01L29/423 , H01L29/10
摘要： A device comprises a vertical transistor. The vertical transistor comprises a semiconductive pillar, at least one gate electrode, a gate dielectric material, and void spaces. The semiconductive pillar comprises a source region, a drain region, and a channel region extending vertically between the source region and the drain region, the channel region comprising a semiconductive material having a band gap greater than 1.65 electronvolts. The at least one gate electrode laterally neighbors the semiconductive pillar. The gate dielectric material is laterally between the semiconductive pillar and the at least one gate electrode. The void spaces are vertically adjacent the gate dielectric material and laterally intervening between the at least one gate electrode and each of the source region and the drain region of the semiconductive pillar. Related electronic systems and methods are also disclosed.

76. 发明授权

US08759895B2 Semiconductor charge storage apparatus and methods 有权
标题翻译：半导体电荷存储装置及方法
公开(公告)号：US08759895B2
公开(公告)日：2014-06-24
申请号：US13035700
申请日：2011-02-25
申请人： Sanh D. Tang , John K. Zahurak
发明人： Sanh D. Tang , John K. Zahurak
IPC分类号： H01L29/788
CPC分类号： H01L27/11556 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11524 , H01L27/11578 , H01L27/11582 , H01L29/04 , H01L29/167 , H01L29/495 , H01L29/4966 , H01L29/7889 , H01L29/792 , H01L29/7926
摘要： Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.
摘要翻译：描述形成多层半导体器件的方法以及包括它们的装置和系统。在一种这样的方法中，在半导体材料层和电介质层中形成开口。通过开口暴露的半导体材料层的一部分被处理，使得该部分与该层中剩余的半导体材料不同地掺杂。至少基本上所有剩余的层的半导体材料被去除，留下半导体材料层的不同掺杂部分作为电荷存储结构。在电荷存储结构的第一表面上形成隧道电介质，并且在电荷存储结构的第二表面上形成隔间电介质。还描述了另外的实施例。

77. 发明授权

US08710583B2 Dual work function recessed access device and methods of forming 有权
标题翻译：双功能凹槽接入设备及其成型方法
公开(公告)号：US08710583B2
公开(公告)日：2014-04-29
申请号：US13196527
申请日：2011-08-02
申请人： Venkatesan Ananthan , Sanh D. Tang
发明人： Venkatesan Ananthan , Sanh D. Tang
IPC分类号： H01L29/94
CPC分类号： H01L29/7827 , H01L29/42376 , H01L29/4966 , H01L29/66621
摘要： A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage current losses from the recessed access device. The gate electrode may include a first gate material having a high work function disposed in a bottom portion of the recessed access device and a second gate material having a lower work function disposed over the first gate material and in an upper portion of the recessed access device.
摘要翻译：具有由具有不同功函数的两个或多个栅极材料形成的栅电极的凹陷存取装置可以减小来自凹陷存取装置的栅极引起的漏极漏电流损耗。栅电极可以包括具有设置在凹陷入口装置的底部中的高功函的第一栅极材料和具有设置在第一栅极材料上的下功函数的第二栅极材料以及凹陷入口装置的上部。

78. 发明申请

US20140054718A1 Arrays of Vertically-Oriented Transistors, And Memory Arrays Including Vertically-Oriented Transistors 有权
标题翻译：垂直定向晶体管阵列，以及包括垂直定向晶体管的存储阵列
公开(公告)号：US20140054718A1
公开(公告)日：2014-02-27
申请号：US13595854
申请日：2012-08-27
申请人： Kamal M. Karda , Shyam Surthi , Wolfgang Mueller , Sanh D. Tang
发明人： Kamal M. Karda , Shyam Surthi , Wolfgang Mueller , Sanh D. Tang
IPC分类号： H01L27/105 , H01L27/10
CPC分类号： H01L27/10876 , H01L21/765 , H01L27/10855
摘要： An array includes vertically-oriented transistors. The array includes rows of access lines and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The array includes a plurality of conductive lines which individually extend longitudinally parallel and laterally between immediately adjacent of the data/sense lines. Additional embodiments are disclosed.
摘要翻译：阵列包括垂直取向的晶体管。该阵列包括访问行和数据/检测行列。这些行的单独包括在该行中互连晶体管的访问线。列的单独包括在该列中互连晶体管的数据/感测线。阵列包括多个导线，它们在紧邻的数据/感测线之间纵向平行且横向延伸。公开了另外的实施例。

79. 发明申请

US20130334483A1 METHODS OF FORMING RESISTIVE MEMORY ELEMENTS AND RELATED RESISTIVE MEMORY ELEMENTS, RESISTIVE MEMORY CELLS, AND RESISTIVE MEMORY DEVICES 有权
标题翻译：形成电阻记忆元件和相关电阻记忆元件，电阻记忆细胞和电阻记忆装置的方法
公开(公告)号：US20130334483A1
公开(公告)日：2013-12-19
申请号：US13523356
申请日：2012-06-14
申请人： D. V. Nirmal Ramaswamy , Sanh D. Tang , Alessandro Torsi , Muralikrishnan Balakrishnan , Xiaonan Chen , John K. Zahurak
发明人： D. V. Nirmal Ramaswamy , Sanh D. Tang , Alessandro Torsi , Muralikrishnan Balakrishnan , Xiaonan Chen , John K. Zahurak
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L45/146 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/1641
摘要： A method of forming a resistive memory element comprises forming an oxide material over a first electrode. The oxide material is exposed to a plasma process to form a treated oxide material. A second electrode is formed on the treated oxide material. Additional methods of forming a resistive memory element, as well as related resistive memory elements, resistive memory cells, and resistive memory devices are also described.
摘要翻译：形成电阻式存储元件的方法包括在第一电极上形成氧化物材料。将氧化物材料暴露于等离子体工艺以形成经处理的氧化物材料。在经处理的氧化物材料上形成第二电极。还描述了形成电阻性存储器元件以及相关的电阻性存储器元件，电阻存储器单元和电阻存储器件的附加方法。

80. 发明授权

US08609492B2 Vertical memory cell 有权
标题翻译：垂直存储单元
公开(公告)号：US08609492B2
公开(公告)日：2013-12-17
申请号：US13192207
申请日：2011-07-27
申请人： Kurt D. Beigel , Sanh D. Tang
发明人： Kurt D. Beigel , Sanh D. Tang
IPC分类号： H01L21/336
CPC分类号： H01L29/0638 , H01L27/1027 , H01L27/10802 , H01L29/0688 , H01L29/7841 , H01L29/78642 , H01L29/7889
摘要： Methods of forming, devices, and apparatus associated with a vertical memory cell are provided. One example method of forming a vertical memory cell can include forming a semiconductor structure over a conductor line. The semiconductor structure can have a first region that includes a first junction between first and second doped materials. An etch-protective material is formed on a first pair of sidewalls of the semiconductor structure above the first region. A volume of the first region is reduced relative to a body region of the semiconductor structure in a first dimension.
摘要翻译：提供了形成装置的方法以及与垂直存储单元相关联的装置。形成垂直存储单元的一个示例性方法可以包括在导体线上形成半导体结构。半导体结构可以具有包括第一和第二掺杂材料之间的第一结的第一区域。在第一区域上方的半导体结构的第一对侧壁上形成蚀刻保护材料。第一区域的体积相对于半导体结构的体区在第一维度上减小。

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