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71. 发明授权

US06768685B1 Integrated circuit memory array with fast test mode utilizing multiple word line selection and method therefor 有权
标题翻译：具有快速测试模式的集成电路存储器阵列，利用多种字线选择及其方法
公开(公告)号：US06768685B1
公开(公告)日：2004-07-27
申请号：US09990894
申请日：2001-11-16
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C700
CPC分类号： G11C29/34 , G11C2029/1202 , G11C2029/2602
摘要： In a programmable memory array, multiple memory cells on a single bit line may be tested in parallel for the unprogrammed state by simultaneously selecting multiple word lines associated with a selected bit line within a sub-array. A read current flowing through each selected memory cell is added on the selected bit line, and may be sensed using the same bit line sense circuits used for normal read operations. In the test mode, the sense circuit preferably indicates a pass/fail condition for all N simultaneously selected memory cells, which may be directly conveyed as an output signal, or may be combined with other similar pass/fail signals from other selected bit line sense circuits to generate a combined pass/fail output signal. Multiple bit lines may be simultaneously selected within the same sub-array. In addition, multiple sub-arrays may be simultaneously selected, each having one or more simultaneously selected bit lines, and the respective pass/fail signals conveyed directly or combined into fewer numbers of such signals.
摘要翻译：在可编程存储器阵列中，通过同时选择与子阵列内的所选位线相关联的多个字线，可以对未编程状态并行测试单个位线上的多个存储器单元。流经每个所选择的存储单元的读取电流被添加到所选择的位线上，并且可以使用用于正常读取操作的相同位线检测电路来感测。在测试模式中，感测电路优选地表示可以直接作为输出信号传送的所有N个同时选择的存储器单元的通过/失败条件，或者可以与来自其他所选位线检测的其他类似的通过/失败信号组合生成组合的通过/失败输出信号的电路。可以在同一子阵列内同时选择多个位线。此外，可以同时选择多个子阵列，每个子阵列具有一个或多个同时选择的位线，并且相应的通过/失败信号被直接传送或组合成较少数量的这种信号。

72. 发明授权

US06735546B2 Memory device and method for temperature-based control over write and/or read operations 有权
标题翻译：用于对写入和/或读取操作进行温度控制的存储器件和方法
公开(公告)号：US06735546B2
公开(公告)日：2004-05-11
申请号：US09944613
申请日：2001-08-31
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G06F1500
CPC分类号： G11C7/04 , G01K3/005
摘要： The preferred embodiments described herein provide a memory device and method for temperature-based control over write and/or read operations. In one preferred embodiment, the temperature of a memory array is monitored, and a write operation to the memory array is prevented in response to the monitored temperature reaching a threshold temperature. In another preferred embodiment, the temperature of a memory array is monitored, and a read operation from the memory array is prevented in response to the monitored temperature reaching a threshold temperature. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
摘要翻译：本文所述的优选实施例提供了一种用于基于写入和/或读取操作的基于温度的控制的存储器件和方法。在一个优选实施例中，监视存储器阵列的温度，并且响应于所监视的温度达到阈值温度来防止对存储器阵列的写入操作。在另一优选实施例中，监视存储器阵列的温度，并且响应于所监视的温度达到阈值温度来防止来自存储器阵列的读取操作。提供了其它优选实施方案，并且每个优选实施方案可以单独使用或彼此组合使用。

73. 发明授权

US06515904B2 Method and system for increasing programming bandwidth in a non-volatile memory device 有权
公开(公告)号：US06515904B2
公开(公告)日：2003-02-04
申请号：US09895960
申请日：2001-06-29
申请人： Christopher S. Moore , Bendik Kleveland , Roger W. March , James M. Cleeves , Roy E. Scheuerlein
发明人： Christopher S. Moore , Bendik Kleveland , Roger W. March , James M. Cleeves , Roy E. Scheuerlein
IPC分类号： G11C1600
CPC分类号： G11C8/08 , G11C7/062 , G11C7/067 , G11C7/18 , G11C16/10 , G11C2207/063
摘要： The preferred embodiments described herein provide a method and system for increasing programming bandwidth in a non-volatile memory device. In one preferred embodiment, a memory device is provided with a plurality of bits to be stored in a respective plurality of memory cells along a wordline. Some of the bits represent a programmed state, and others represent an un-programmed state. The duration of the programming pulse applied to the wordline is determined by the number of bits that represent the programmed state. In another preferred embodiment, the plurality of bits to be stored in the memory device comprises a first set of bits representing a modification to the stored data and a second set of bits representing an un-programmed state. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

74. 发明授权

US06504753B1 Method and apparatus for discharging memory array lines 有权
标题翻译：用于放电存储器阵列线的方法和装置
公开(公告)号：US06504753B1
公开(公告)日：2003-01-07
申请号：US09897784
申请日：2001-06-29
申请人： Roy E. Scheuerlein , Matthew P. Crowley
发明人： Roy E. Scheuerlein , Matthew P. Crowley
IPC分类号： G11C1136
CPC分类号： G11C8/08 , G11C7/062 , G11C7/067 , G11C7/18 , G11C2207/063
摘要： A passive element memory array preferably biases selected X-lines to an externally received VPP voltage and selected Y-lines to ground. Unselected Y-lines are preferably biased to VPP minus a first offset voltage, and unselected X-lines biased to a second offset voltage (relative to ground). The first and second offset voltages preferably are identical and have a value of about 0.5 to 2 volts. The VPP voltage depends upon the memory cell technology used, and preferably falls within the range of 5 to 20 volts. The area otherwise required for an on-chip VPP generator and saves the power that would be consumed by such a generator. In addition, the operating temperature of the integrated circuit during the programming operation decreases, which further decreases power dissipation. When discharging the memory array, the capacitance between layers is preferably discharged first, then the layers are discharged to ground.
摘要翻译：无源元件存储器阵列优选地将所选择的X线偏置到外部接收的VPP电压，并将选定的Y线偏置到地。未选择的Y线优选地偏置到VPP减去第一偏移电压，并且偏置到第二偏移电压（相对于地）的未选择的X线。第一和第二偏移电压优选地相同并且具有约0.5至2伏特的值。 VPP电压取决于所使用的存储器单元技术，优选落在5至20伏的范围内。片上VPP发生器所需的区域，并节省了这种发电机将消耗的功率。此外，编程操作期间集成电路的工作温度降低，这进一步降低了功耗。当放电存储器阵列时，层间的电容最好首先放电，然后将这些层放电到地。

75. 再颁专利

USRE32236E One device field effect transistor (FET) AC stable random access memory (RAM) array 失效
标题翻译：一个器件场效应晶体管（FET）AC稳定随机存取存储器（RAM）阵列
公开(公告)号：USRE32236E
公开(公告)日：1986-08-26
申请号：US763171
申请日：1985-08-07
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C5/06 , G11C11/403 , G11C11/4097
CPC分类号： G11C5/063 , G11C11/403 , G11C11/4097
摘要： Disclosed is an integrated circuit electrode memory array having a plurality of FET memory cells arranged in rows and columns and formed on the same integrated circuit chip with associated support circuits. Each memory cell of the array has a capacitive storage region, an adjacent channel region, and a gate region for controlling the transfer of binary information through the channel region in and out of the capacitive storage region. Each memory cell also has a bit line contact region which is shared with an adjacent memory cell. The word lines are arranged in rows in a substantially equidistant parallel relationship, each word line passing, in succession, over the storage region of a first one of the memory cells and electrically integral with the gate region of a second one of the memory cells. The column arrangement of memory cells is interdigitated such that the memory cells associated with a single bit line are arranged in first and second parallel lines along both the left and right sides of each bit line. Thus, the bit line is arranged in a zig-zag configuration alternatively contacting memory cells arranged along its left and right side.

76. 发明授权

US08679967B2 Apparatus and methods of forming memory lines and structures using double sidewall patterning for four times half pitch relief patterning 有权
标题翻译：使用双侧壁图案形成存储器线和结构的装置和方法，用于四次半间距浮雕图案化
公开(公告)号：US08679967B2
公开(公告)日：2014-03-25
申请号：US12911887
申请日：2010-10-26
申请人： Roy E. Scheuerlein , Yoichiro Tanaka
发明人： Roy E. Scheuerlein , Yoichiro Tanaka
IPC分类号： H01L21/4763
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.
摘要翻译：本发明提供用于制造使用双重侧壁图案化四次半间距浮雕图案化的存储器线和结构的装置，方法和系统。本发明包括从设置在基板上方的第一模板层形成特征，形成邻近特征的半间距侧壁间隔，通过使用半间距侧壁间隔物作为硬掩模在第二模板层中形成更小的特征，形成四分之一间距侧壁靠近较小特征的间隔物，并且通过使用四分之一间距侧壁间隔物作为硬掩模，从导体层形成导体特征。公开了许多附加方面。

77. 发明授权

US08659028B2 Three-dimensional memory device incorporating segmented array line memory array 有权
公开(公告)号：US08659028B2
公开(公告)日：2014-02-25
申请号：US11764789
申请日：2007-06-18
申请人： Roy E. Scheuerlein , Alper Ilkbahar , Luca G. Fasoli
发明人： Roy E. Scheuerlein , Alper Ilkbahar , Luca G. Fasoli
IPC分类号： H01L27/10
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/0466 , G11C17/12 , G11C17/18 , G11C2213/71 , G11C2213/77 , Y10S257/91
摘要： A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.

78. 发明授权

US08649206B2 Multi-bit resistance-switching memory cell 有权
标题翻译：多位电阻切换存储单元
公开(公告)号：US08649206B2
公开(公告)日：2014-02-11
申请号：US13396489
申请日：2012-02-14
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C13/0069 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A non-volatile storage apparatus comprises a set of Y lines, a set of X lines and a plurality of memory cells in communication with the set of X lines and the set of Y lines. Each memory cell of the plurality of memory cells includes a resistance element in a static resistance condition and two or more reversible resistance-switching elements. The resistance element in the static resistance condition and the two or more reversible resistance-switching elements are connected to different Y lines of the set of Y lines. The resistance element in the low resistance state and the two or more reversible resistance-switching elements are connected to a common X line of the set of X lines. One or multiple bits of data are programmed into a particular memory cell of the plurality of memory cells by causing current flow between Y lines connected to the particular memory cell.
摘要翻译：非易失性存储装置包括一组Y线，一组X线和与该X线组和Y线组通信的多个存储单元。多个存储单元的每个存储单元包括静态电阻状态的电阻元件和两个或多个可逆电阻切换元件。静态电阻状态下的电阻元件和两个以上的可逆电阻切换元件被连接到该Y线组的不同Y线。低电阻状态下的电阻元件和两个或更多个可逆电阻切换元件连接到该X线组的公共X线。一个或多个数据位通过在连接到特定存储单元的Y线之间引起电流而编程到多个存储单元的特定存储单元中。

79. 发明授权

US08618614B2 Continuous mesh three dimensional non-volatile storage with vertical select devices 有权
标题翻译：连续网格三维非易失性存储与垂直选择设备
公开(公告)号：US08618614B2
公开(公告)日：2013-12-31
申请号：US13323680
申请日：2011-12-12
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： H01L27/088
CPC分类号： G11C13/0033 , G11C5/025 , G11C8/08 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C13/0069 , H01L27/0688 , H01L27/115 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/165 , H01L45/1683
摘要： A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
摘要翻译：适用于响应于在其上施加电压差而可逆地改变电导水平的存储器元件的三维阵列。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件所连接的位线从衬底垂直定向并穿过多个平面。

80. 发明授权

US08531904B2 Methods and apparatus for extending the effective thermal operating range of a memory 有权
标题翻译：扩展存储器的有效热操作范围的方法和装置
公开(公告)号：US08531904B2
公开(公告)日：2013-09-10
申请号：US13205820
申请日：2011-08-09
申请人： Tyler J. Thorp , Roy E. Scheuerlein
发明人： Tyler J. Thorp , Roy E. Scheuerlein
IPC分类号： G11C7/04
CPC分类号： G11C7/04 , G11C16/06
摘要： Apparatus and systems are provided for thermal regulation of a memory integrated circuit (“IC”). The apparatus and systems may include a thermal sensor on a memory IC, and a heating element coupled to the thermal sensor. The heating element is adapted to heat the memory IC in response to a signal from the thermal sensor. Other aspects are also provided.
摘要翻译：提供了用于存储器集成电路（“IC”）的热调节的装置和系统。该装置和系统可以包括存储器IC上的热传感器和耦合到热传感器的加热元件。加热元件适于响应于来自热传感器的信号来加热存储器IC。还提供其他方面。

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