专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20100044792A1 Charged balanced devices with shielded gate trench 有权
标题翻译：带屏蔽栅极沟槽的均衡器件
公开(公告)号：US20100044792A1
公开(公告)日：2010-02-25
申请号：US12321435
申请日：2009-01-21
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0873 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/66734
摘要： This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super-junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown.
摘要翻译：本发明公开了一种设置在半导体衬底上的半导体功率器件，包括具有填充所述深沟槽的外延层的多个深沟槽和覆盖半导体衬底上的所述深沟槽的顶表面之上的区域的同时生长的顶部外延层。设置在所述顶部外延层中的多个沟槽MOSFET单元，顶部外延层用作体区，并且半导体衬底用作漏极区域，由此通过深沟槽中的外延层之间的电荷平衡实现超结效应以及半导体衬底中与深沟槽横向相邻的区域。每个沟槽MOSFET单元还包括沟槽栅极和栅极屏蔽掺杂剂区域，其设置在用于每个沟槽MOSFET单元的每个沟槽栅极的下方并基本对齐，用于在电压击穿期间屏蔽沟槽栅极。

72. 发明申请

US20100044791A1 Configurations and methods for manufacturing charge balanced devices 有权
公开(公告)号：US20100044791A1
公开(公告)日：2010-02-25
申请号：US12229250
申请日：2008-08-20
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0623 , H01L29/0634 , H01L29/0873 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/66734
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material.

73. 发明申请

US20100024213A1 COPPER BONDING METHOD 有权
标题翻译：铜接合方法
公开(公告)号：US20100024213A1
公开(公告)日：2010-02-04
申请号：US12541881
申请日：2009-08-14
申请人： Francois Hebert , Anup Bhalla
发明人： Francois Hebert , Anup Bhalla
IPC分类号： H01R43/02
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05017 , H01L2224/05073 , H01L2224/05124 , H01L2224/05147 , H01L2224/05556 , H01L2224/05624 , H01L2224/0603 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/48624 , H01L2224/48724 , H01L2224/48824 , H01L2224/85201 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device.
摘要翻译：公开了一种铜键合兼容的键合焊盘结构及其相关方法。器件接合焊盘结构包括由互连金属的区域和非导电钝化材料的区域形成的缓冲结构，该缓冲结构为器件的下层和结构提供缓冲。

74. 发明申请

US20090242973A1 SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON 审中-公开
标题翻译：使用POLYSILICON的TRENCH-DMOS器件的源和体接触结构
公开(公告)号：US20090242973A1
公开(公告)日：2009-10-01
申请号：US12060096
申请日：2008-03-31
申请人： Francois Hebert , Anup Bhalla
发明人： Francois Hebert , Anup Bhalla
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/086 , H01L29/0869 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734
摘要： A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed.
摘要翻译：半导体器件包括栅极电极，设置在栅电极旁边的顶部源极区域，设置在栅极电极底部的漏极区域，设置在源极区域和栅极电极顶部的氧化物以及掺杂多晶硅间隔物沿着源区域的侧壁和氧化物的侧壁设置。还公开了制造这种装置的方法。

75. 发明申请

US20090134964A1 Lead frame-based discrete power inductor 有权
标题翻译：引线框架分立功率电感
公开(公告)号：US20090134964A1
公开(公告)日：2009-05-28
申请号：US12011489
申请日：2008-01-25
申请人： Francois Hebert , Tao Feng , Xiaotian Zhang , Jun Lu
发明人： Francois Hebert , Tao Feng , Xiaotian Zhang , Jun Lu
IPC分类号： H01F5/00
CPC分类号： H01F17/062
摘要： A lead frame-based discrete power inductor is disclosed. The power inductor includes top and bottom lead frames, the leads of which form a coil around a single closed-loop magnetic core. The coil includes interconnections between inner and outer contact sections of the top and bottom lead frames, the magnetic core being sandwiched between the top and bottom lead frames. Ones of the leads of the top and bottom lead frames have a generally non-linear, stepped configuration such that the leads of the top lead frame couple adjacent leads of the bottom lead frame about the magnetic core to form the coil.
摘要翻译：公开了一种基于引线框架的分立功率电感器。功率电感器包括顶部和底部引线框架，其引线围绕单个闭环磁芯形成线圈。线圈包括顶部和底部引线框架的内部和外部接触部分之间的互连，磁芯夹在顶部和底部引线框架之间。顶部引线框架和底部引线框架的引线的一部分具有大致非线性的阶梯状构造，使得顶部引线框架的引线将底部引线框架的相邻引线围绕磁芯耦合以形成线圈。

76. 发明申请

US20080238599A1 Chip scale power converter package having an inductor substrate 有权
标题翻译：具有电感器基板的芯片级功率转换器封装
公开(公告)号：US20080238599A1
公开(公告)日：2008-10-02
申请号：US11729311
申请日：2007-03-27
申请人： Francois Hebert , Ming Sun
发明人： Francois Hebert , Ming Sun
IPC分类号： H01F17/04 , H01F27/28
CPC分类号： H01L23/645 , H01L23/5227 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/13091 , H01L2924/1461 , H01L2924/1902 , H01L2924/3025 , Y10T29/4902 , Y10T29/49075 , H01L2924/00 , H01L2224/0401
摘要： A chip scale power converter package having an inductor substrate and a power integrated circuit flipped onto the inductor substrate is disclosed. The inductor substrate includes a high resistivity substrate having a planar spiral inductor formed thereon.
摘要翻译：公开了一种具有电感器基板和翻转到电感器基板上的功率集成电路的芯片级功率转换器封装。电感器基板包括其上形成有平面螺旋电感器的高电阻率基板。

77. 发明申请

US20070035906A1 Transient blocking unit 审中-公开
标题翻译：瞬态阻断单位
公开(公告)号：US20070035906A1
公开(公告)日：2007-02-15
申请号：US11503357
申请日：2006-08-10
申请人： Richard Harris , Richard Blanchard , Francois Hebert
发明人： Richard Harris , Richard Blanchard , Francois Hebert
IPC分类号： H02H9/06
CPC分类号： H02H9/025
摘要： Improved electrical transient blocking is provided with a transient blocking unit (TBU) having a partial disconnect capability. A TBU is an arrangement of voltage controlled switches that normally conducts, but switches to a disconnected state in response to an above-threshold input transient. Partial disconnection improves the power handling capability of a TBU by preventing thermal damage to the TBU. Partial TBU disconnection can be implemented to keep power dissipation in the TBU below a predetermined level Pmax, thereby avoiding thermal damage to the TBU by keeping the TBU temperature below a temperature limit Tmax. Alternatively, partial TBU disconnection can be implemented to keep TBU temperature below Tmax using direct temperature sensing and feedback.
摘要翻译：提供了具有部分断开能力的瞬态阻塞单元（TBU）的改进的电气瞬态阻塞。 TBU是通常导通的电压控制开关的布置，但是响应于高于阈值的输入瞬变而切换到断开状态。部分断开通过防止TBU的热损坏提高了TBU的功率处理能力。可以实施部分TBU断开以将TBU中的功率消耗降低到预定水平P max以下，从而通过将TBU温度保持在温度下限T max以下来避免对TBU的热损伤， SUB>。或者，可以使用直接温度感测和反馈来实现部分TBU断开以将TBU温度保持在T 以下。

78. 发明申请

US20060158812A1 Transient blocking unit having shunt for over-voltage protection 审中-公开
标题翻译：瞬态阻塞单元具有分流以进行过电压保护
公开(公告)号：US20060158812A1
公开(公告)日：2006-07-20
申请号：US11331836
申请日：2006-01-12
申请人： Richard Harris , Francois Hebert
发明人： Richard Harris , Francois Hebert
IPC分类号： H02H3/22
CPC分类号： H02H9/025 , H01L27/0266 , H02H9/04
摘要： A transient blocking unit (TBU) having improved damage resistance is provided. A TBU includes two or more depletion mode transistors arranged to provide a low series impedance in normal operation and a high series impedance when the input current exceeds a predetermined threshold. At least one of the TBU transistors is a protecting device having a shunt circuit element connected in parallel with its channel. When the TBU is in its high impedance state, the shunt circuit element provides a current path, thereby decreasing terminal voltages on at least one of the TBU transistors. The shunt element can be a discrete or integrated resistor, a current source including a transistor, or an appropriately engineered device parasitic.
摘要翻译：提供了具有改善的耐损伤性的瞬态阻断单元（TBU）。 TBU包括两个或多个耗尽型晶体管，其布置成在正常操作中提供低串联阻抗，并且当输入电流超过预定阈值时包括高串联阻抗。 TBU晶体管中的至少一个是具有与其沟道并联连接的分流电路元件的保护器件。当TBU处于高阻抗状态时，分流电路元件提供电流路径，从而减小至少一个TBU晶体管的端电压。分路元件可以是分立或集成的电阻器，包括晶体管的电流源或者适当设计的器件寄生的。

79. 发明申请

US20060098364A1 Apparatus and method for enhanced transient blocking 有权
标题翻译：用于增强瞬态阻塞的装置和方法
公开(公告)号：US20060098364A1
公开(公告)日：2006-05-11
申请号：US11270062
申请日：2005-11-08
申请人： Richard Harris , Francois Hebert
发明人： Richard Harris , Francois Hebert
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H02H5/042 , H02H5/044 , H02H9/025 , H02H9/046
摘要： An apparatus and method for enhanced transient blocking employing a transient blocking unit (TBU) that uses at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device. The interconnection is performed such that a transient alters a bias voltage Vp of the p-channel device and a bias voltage Vn of the n-channel device such that the p- and n-channel devices mutually switch off to block the transient. The apparatus has an enhancer circuit for applying an enhancement bias to a gate terminal of at least one of the depletion mode n-channel devices of the TBU to reduce a total resistance Rtot of the apparatus. Alternatively, the apparatus has an enhancement mode NMOS transistor and a TBU connected thereto to help provide an enhancement bias to a gate terminal of the enhancement mode NMOS.
摘要翻译：一种用于增强瞬态阻塞的装置和方法，其采用使用与至少一个耗尽型p沟道器件互连的至少一个耗尽型n沟道器件的瞬态阻塞单元（TBU）。执行互连，使得瞬态改变p沟道器件的偏置电压V P和N沟道器件的偏置电压V N n N，使得p - 和n通道设备相互关闭以阻止瞬态。该装置具有增强器电路，用于向TBU中的至少一个耗尽型n沟道器件的栅极端子施加增强偏置，以减小器件的总电阻R tht。或者，该装置具有增强型NMOS晶体管和与其连接的TBU，以帮助向增强型NMOS的栅极端提供增强偏置。

80. 发明授权

US06797549B2 High voltage MOS transistor with gate extension 有权
标题翻译：具有栅极延伸的高压MOS晶体管
公开(公告)号：US06797549B2
公开(公告)日：2004-09-28
申请号：US10272688
申请日：2002-10-15
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L2100
CPC分类号： H01L29/402 , H01L29/42376 , H01L29/7835
摘要： A high voltage MOS transistor with a gate extension that has a reduced electric field in the drain region near the gate is provided. The high voltage MOS transistor includes a first and second gate layers, and a dielectric layer between the gate layers. The first and second gate layers are electrically coupled together and form the gate of the transistor. The second gate layer extends over the drain of the transistor above the dielectric and gate oxide layers to form the gate extension. The gate extension reduces the peak electric field in the drain by providing a wide area for the voltage to drop between the drain and the gate of the transistor. The dielectric layer also reduces the peak electric field in the drain near the gate by providing insulation between the gate and the drain. A lower electric field in the drain reduces the impact generation rate of carriers. The high voltage MOS transistor of the present invention may be fabricated without additional processing steps in BiCMOS and CMOS processes that use dual polysilicon layers and a dielectric layer that are used to form capacitors.
摘要翻译：提供具有在栅极附近的漏极区域中具有减小的电场的栅极延伸的高压MOS晶体管。高压MOS晶体管包括第一和第二栅极层以及栅极层之间的介电层。第一和第二栅极层电耦合在一起并形成晶体管的栅极。第二栅极层在电介质和栅极氧化物层上方的晶体管的漏极上延伸以形成栅极延伸。门极延伸通过为晶体管的漏极和栅极之间的电压降提供一个宽的面积来减小漏极中的峰值电场。电介质层还通过在栅极和漏极之间提供绝缘来减小栅极附近的漏极中的峰值电场。漏极中较低的电场降低了载流子的冲击产生速率。本发明的高电压MOS晶体管可以在不使用BiCMOS和CMOS工艺中的附加处理步骤的情况下制造，所述工艺使用双重多晶硅层和用于形成电容器的电介质层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式